Hyunjin Lee

ACM Trans. Archit. Code Optim., 2011

CloudCache: Expanding and shrinking private caches.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010

PERFECTORY: A Fault-Tolerant Directory Memory Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2010

StimulusCache: Boosting performance of chip multiprocessors with excess cache.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009

Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance.

[BibT_eX]

[DOI]

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008

TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007

Performance of Graceful Degradation for Cache Faults.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Exploring the interplay of yield, area, and performance in processor caches.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

2006

A flexible data to L2 cache mapping approach for future multicore processors.

[BibT_eX]

[DOI]

Lei Jin