J. Robert Heath
Affiliations:- University of Kentucky, Department of Electrical and Computer Engineering, Lexington, KY, USA
According to our database1,
J. Robert Heath
authored at least 22 papers
between 1977 and 2011.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2011, "For contributions to multiple antenna wireless communications".
Timeline
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Bibliography
2011
FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
2010
A new multichannel, coherent amplitude modulated, time-division multiplexed, software-defined radio receiver architecture, and field-programmable-gate-array technology implementation.
IEEE Trans. Signal Process., 2010
2009
A New Reconfigurable Network Node Processor Architecture for Distributed Implementation of Ephemeral State Processing.
Proceedings of the 22nd International Conference on Parallel and Distributed Computing and Communication Systems, 2009
Development and Validation of a Load Balancing and Control Mechanism for a Reconfigurable Single-Chip Heterogenous and Hybrid Multiprocessor Architecture Platform.
Proceedings of the 22nd International Conference on Parallel and Distributed Computing and Communication Systems, 2009
2008
A Hand-Held Programmable-Logic-Device Based Temperature and Relative-Humidity Sensor, Processor and Display System Platform for Automation and Control of Industry Processes.
Proceedings of the Industry Applications Society Annual Meeting, 2008
2007
New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets.
J. Electronic Imaging, 2007
2004
Proceedings of IEEE International Conference on Communications, 2004
2001
Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
2000
IEEE Netw., 2000
1997
Development, Analysis, and Verification of a Parallel Hybrid Dataflow Computer Architectural Framework and Associated Load-Balancing Strategies and Algorithms via Parallel Simulation.
Simul., 1997
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
1992
Proceedings of the Second Great Lakes Symposium on VLSI, 1992
1988
A methodology for the control and custom VLSI implementation of large-scale Clos networks.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
1986
A note on "Realization of digital filters using input-scaled floating-point arithmetic".
IEEE Trans. Acoust. Speech Signal Process., 1986
1984
An Integrated-Circuit Crossbar Switching System Design.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984
1983
Classification Categories and Historical Development of Circuit Switching Topologies.
ACM Comput. Surv., 1983
1982
A Hardware Task Scheduling Mechanism for a Real-Time Multi-Microprocessor Architecture.
Proceedings of the Real-Time Systems Symposium, 1982
The Design of a Fault-Tolerant Computing Element for Distributed Data Processors.
Proceedings of the Proceedings of the 3rd International Conference on Distributed Computing Systems, 1982
A distributed computer architecture for real-time, data driven applications.
Proceedings of the Proceedings of the 3rd International Conference on Distributed Computing Systems, 1982
1981
1980
The Complexity and Use of a Multistage Interconnection Network for Distributed Processing Systems.
Proceedings of the Distributed Data Acquisition, Computing, and Control Symposium, 1980
1977
Proceedings of the 14th Design Automation Conference, 1977