Jaco A. Hofmann

Orcid: 0000-0003-3691-3293

According to our database1, Jaco A. Hofmann authored at least 12 papers between 2016 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2021
The TaPaSCo Open-Source Toolflow.
J. Signal Process. Syst., 2021

Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design.
Proceedings of the 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers, 2020

2019
High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud.
Proceedings of the 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2019

A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Online Reprogrammable Multi Tenant Switches.
Proceedings of the 1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms, 2019

The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

High-Performance In-Network Data Processing.
Proceedings of the 10th International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2019

2017
Synthesis of interleaved multithreaded accelerators from OpenMP loops.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016
A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching.
Proceedings of the 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2016


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