Julian Oppermann

According to our database1, Julian Oppermann authored at least 18 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Active Storage.
Proceedings of the Encyclopedia of Big Data Technologies., 2019

Exact and Practical Modulo Scheduling for High-Level Synthesis.
TRETS, 2019

SpExSim: assessing kernel suitability for C-based high-level hardware synthesis.
The Journal of Supercomputing, 2019

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.
Proceedings of the Euro-Par 2019: Parallel Processing, 2019

Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

2018
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

ILP-Based Modulo Scheduling and Binding for Register Minimization.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management.
Proceedings of the 21th International Conference on Extending Database Technology, 2018

GeMS: a generator for modulo scheduling problems: work in progress.
Proceedings of the International Conference on Compilers, 2018

Improved High-Level Synthesis for Complex CellML Models.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Synthesis of interleaved multithreaded accelerators from OpenMP loops.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016
Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models.
Concurrency and Computation: Practice and Experience, 2016

Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis.
Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

ILP-based modulo scheduling for high-level synthesis.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Automatic high-level synthesis of multi-threaded hardware accelerators.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Hardware/software co-compilation with the Nymble system.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013


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