Jaesuk Sung

According to our database, Jaesuk Sung authored at least 2 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Highly Digital 143.2-dB DR Sub-1° Phase Error Impedance Monitoring IC With Pulsewidth Modulation Frontend.

Hyeonho Han, Byungchoul Park, Jaesuk Sung, Heonjin Choi, Youngcheol Chae

IEEE J. Solid State Circuits, April, 2024

2023

A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution.

Hyeonho Han, Woojun Choi, Jaehyun Kim, Jaesuk Sung, Heonjin Choi, Youngcheol Chae

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023