JaeWoong Chung

According to our database1, JaeWoong Chung authored at least 22 papers between 1999 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
THEMIS: A Mutually Verifiable Billing System for the Cloud Computing Environment.
IEEE Trans. Serv. Comput., 2013

2011
Optimizing the Concurrent Execution of Locks and Transactions.
Proceedings of the Languages and Compilers for Parallel Computing, 2011

2010
Analysis on semantic transactional memory footprint for hardware transactional memory.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

2009
Fast memory snapshot for concurrent programmingwithout synchronization.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
Improving software concurrency with hardware-assisted memory snapshot.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

Ased: availability, security, and debugging support usingtransactional memory.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

STAMP: Stanford Transactional Applications for Multi-Processing.
Proceedings of the 4th International Symposium on Workload Characterization (IISWC 2008), 2008

Thread-safe dynamic binary translation using transactional memory.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
Transactional Memory: The Hardware-Software Interface.
IEEE Micro, 2007

Towards soft optimization techniques for parallel cognitive applications.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

An effective hybrid transactional memory system with strong isolation guarantees.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Executing Java programs with transactional memory.
Sci. Comput. Program., 2006

The Atomos transactional programming language.
Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, 2006

Architectural Semantics for Practical Transactional Memory.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

The common case transactional behavior of multithreaded programs.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Tradeoffs in transactional memory virtualization.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006

2005
TAPE: a transactional application profiling environment.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Characterization of TCC on Chip-Multiprocessors.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2001
Efficient Fine-Grain Sharing Support for Software DSMs Through Segmentation.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

2000
Boosting superpage utilization with the shadow memory and the partial-subblock TLB.
Proceedings of the 14th international conference on Supercomputing, 2000

1999
Extended Synchronous Dataflow for Efficient DSP System Prototyping.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Moving Home-Based Lazy Release Consistency for Shared Virtual Memory Systems.
Proceedings of the International Conference on Parallel Processing 1999, 1999


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