Soonhoi Ha

According to our database1, Soonhoi Ha authored at least 168 papers between 1991 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to hardware/software codesign".

Timeline

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Bibliography

2019
Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT Analysis.
ACM Trans. Design Autom. Electr. Syst., 2019

Low-Power Computer Vision: Status, Challenges, and Opportunities.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

2018 Embedded Systems Week (ESWEEK) in Torino.
IEEE Design & Test, 2019

Fast Performance Estimation and Design Space Exploration of Manycore-based Neural Processors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
SeMo: Service-Oriented and Model-Based Software Framework for Cooperating Robots.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A hybrid performance analysis technique for distributed real-time embedded systems.
Real-Time Systems, 2018

The 2017 Embedded Systems Week (ESWEEK).
IEEE Design & Test, 2018

Fast parallel simulation of a manycore architecture with a flit-level on-chip network model.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

C-GOOD: C-code generation framework for optimized on-device deep learning.
Proceedings of the International Conference on Computer-Aided Design, 2018

Joint optimization of speed, accuracy, and energy for embedded image recognition systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

End-to-end latency analysis of cause-effect chains in an engine management system.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

NNsim: fast performance estimation based on sampled simulation of GPGPU kernels for neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

Embedded Software Design Methodology Based on Formal Models of Computation.
Proceedings of the Principles of Modeling, 2018

Service-Oriented Robot Software Development Framework for Distributed Heterogeneous Platforms.
Proceedings of the 17th International Conference on Autonomous Agents and MultiAgent Systems, 2018

Architectures and algorithms for user customization of CNNs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Introduction to Hardware/Software Codesign.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

HOPES: Programming Platform Approach for Embedded Systems Design.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Multiprocessor Scheduling of a Multi-Mode Dataflow Graph Considering Mode Transition Delay.
ACM Trans. Design Autom. Electr. Syst., 2017

Worst-Case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-Time Tasks.
ACM Trans. Design Autom. Electr. Syst., 2017

A novel service-oriented platform for the internet of things.
Proceedings of the Seventh International Conference on the Internet of Things, 2017

FIFA: A Kernel-Level Fault Injection Framework for ARM-Based Embedded Linux System.
Proceedings of the 2017 IEEE International Conference on Software Testing, 2017

Worst case delay analysis of shared resource access in partitioned multi-core systems.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

Hierarchical Dataflow Modeling of Iterative Applications.
Proceedings of the 54th Annual Design Automation Conference, 2017

A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

Incremental training of CNNs for user customization: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

2016
A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Power Optimization of Multimode Mobile Embedded Systems with Workload-Delay Dependency.
Mobile Information Systems, 2016

SoPHy+: Programming model and software platform for hybrid resource management of many-core accelerators.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

TQSIM: A fast cycle-approximate processor simulator based on QEMU.
Journal of Systems Architecture - Embedded Systems Design, 2016

An Adaptive Frames Per Second-Based CPU-GPU Cooperative Dynamic Voltage and Frequency Scaling Governing Technique for Mobile Games.
J. Low Power Electronics, 2016

Multiprocessor Scheduling of an SDF Graph with Library Tasks Considering the Worst Case Contention Delay.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Real-time co-scheduling of multiple dataflow graphs on multi-processor systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening.
IEEE Trans. Computers, 2015

Fast GPU-in-the-loop simulation technique at OpenGL ES API level for Android Graphics Applications.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Modeling and power optimization of cyber-physical systems with energy-workload tradeoff.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems: HOPES Approach.
ACM Trans. Embedded Comput. Syst., 2014

System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

An efficient parallelization technique for x264 encoder on heterogeneous platforms consisting of CPUs and GPUs.
J. Real-Time Image Processing, 2014

SoPHy: A Software Platform for Hybrid Resource Management of Homogeneous Many-core Accelerators.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014

Hardware-in-the-loop simulation of Android GPGPU applications.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Software platform for hybrid resource management of a many-core accelerator for multimedia applications.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Parallelization and performance prediction for HEVC UHD real-time software decoding.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Reliability-aware mapping optimization of multi-core systems with mixed-criticality.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Decidable Dataflow Models for Signal Processing: Synchronous Dataflow and Its Extensions.
Proceedings of the Handbook of Signal Processing Systems, 2013

Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints.
Signal Processing Systems, 2013

Efficient run-time resource management of a manycore accelerator for stream-based applications.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

A novel analytical method for worst case response time estimation of distributed embedded systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Prolog to the Section on Hardware/Software Codesign.
Proceedings of the IEEE, 2012

A parallel and distributed meta-heuristic framework based on partially ordered knowledge sharing.
J. Parallel Distrib. Comput., 2012

Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC.
Design Autom. for Emb. Sys., 2012

An ILP-based Worst-case Performance Analysis Technique for Distributed Real-time Embedded Systems.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012

A cycle-level parallel simulation technique exploiting both space and time parallelism.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Multi-objective mapping optimization via problem decomposition for many-core systems.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

Executing synchronous dataflow graphs on a SPM-based multicore architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Library Support in an Actor-Based Parallel Programming Platform.
IEEE Trans. Industrial Informatics, 2011

Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Software synthesis in the ESL methodology for multicore embedded systems.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Automatic CUDA Code Synthesis Framework for Multicore CPU and GPU Architectures.
Proceedings of the Parallel Processing and Applied Mathematics, 2011

Resource minimized static mapping and dynamic scheduling of SDF graphs.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

An efficient parallel motion estimation algorithm and X264 parallelization in CUDA.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Simulation environment configuration for parallel simulation of multicore embedded systems.
Proceedings of the 48th Design Automation Conference, 2011

Mapping of applications to MPSoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification.
Signal Processing Systems, 2010

Serialized parallel code generation framework for MPSoC.
ACM Trans. Design Autom. Electr. Syst., 2010

An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

An Application Framework for Loosely Coupled Networked Cyber-Physical Systems.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010

Task-level timed-functional simulation for multi-core embedded systems.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

A task remapping technique for reliable multi-core embedded systems.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Decidable Signal Processing Dataflow Graphs: Synchronous and Cyclo-Static Dataflow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Boolean circuit programming: A new paradigm to design parallel algorithms.
J. Discrete Algorithms, 2009

A timed HW/SW coemulation technique for fast yet accurate system verification.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Introduction.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

Pipelined data parallel task mapping/scheduling technique for MPSoC.
Proceedings of the Design, Automation and Test in Europe, 2009

Programming MPSoC platforms: Road works ahead!
Proceedings of the Design, Automation and Test in Europe, 2009

On-chip communication architecture exploration for processor-pool-based MPSoC.
Proceedings of the Design, Automation and Test in Europe, 2009

Scalable and retargetable simulation techniquesfor multiprocessor systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis.
Signal Processing Systems, 2008

A retargetable parallel-programming framework for MPSoC.
ACM Trans. Design Autom. Electr. Syst., 2008

Introduction to embedded systems week 2006 special issue.
ACM Trans. Embedded Comput. Syst., 2008

Overcoming performance bottlenecks in using OpenMP on SMP clusters.
Parallel Computing, 2008

Serialized multitasking code generation from dataflow specification.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Automatic H.264 encoder synthesis for the Cell processor from a target independent specification.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Architecture Exploration of NAND Flash-based Multimedia Card.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
PeaCE: A hardware-software codesign environment for multimedia embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2007

Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Communication Architecture Simulation on the Virtual Synchronization Framework.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Performance Analysis of Parallel Execution of H.264 Encoder on the Cell Processor.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Data-Parallel Code Generation from Synchronous Dataflow Specification of Multimedia Applications.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

A novel technique to use scratch-pad memory for stack management.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

CATS: cycle accurate transaction-driven simulation with multiple processor simulators.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems.
Proceedings of the 2007 International Conference on Compilers, 2007

Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Model-based Programming Environment of Embedded Software for MPSoC.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Efficient exploration of bus-based system-on-chip architectures.
IEEE Trans. VLSI Syst., 2006

Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

Improving Performance of OpenMP for SMP Clusters Through Overlapped Page Migrations.
Proceedings of the OpenMP Shared Memory Parallel Programming - International Workshops, 2006

Dynamic code overlay of SDF-modeled programs on low-end embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Parallel co-simulation using virtual synchronization with redundant host execution.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Conversion of reference C code to dataflow model: H.264 encoder case study.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Formalization of fFSM Model and Its Verification.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Trace-driven HW/SW cosimulation using virtual synchronization technique.
Proceedings of the 42nd Design Automation Conference, 2005

Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.
Proceedings of the 2005 International Conference on Compilers, 2005

Embedded software generation from system level specification for multi-tasking embedded systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Static analysis and automatic code synthesis of flexible FSM model.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Fractional Rate Dataflow Model for Efficient Code Synthesis.
VLSI Signal Processing, 2004

Dynamic voltage scheduling with buffers in low-power multimedia applications.
ACM Trans. Embedded Comput. Syst., 2004

Memory management for multi-threaded software DSM systems.
Parallel Computing, 2004

Energy Optimization for Latency- and Quality-Constrained Video Applications.
IEEE Design & Test of Computers, 2004

Atomic Page Update Methods for OpenMP-Aware Software DSM.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004

Dynamic voltage scaling for real-time multi-task scheduling using buffers.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Fast design space exploration framework with an efficient performance estimation technique.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

Efficient exploration of on-chip bus architectures and memory allocation.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Memory-Optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples.
EURASIP J. Adv. Sig. Proc., 2003

Fast and Time-Accurate Cosimulation with OS Scheduler Modeling.
Design Autom. for Emb. Sys., 2003

Design and implementation of a user-level Sockets layer over Virtual Interface Architecture.
Concurrency and Computation: Practice and Experience, 2003

ParADE: An OpenMP Programming Environment for SMP Cluster Systems.
Proceedings of the ACM/IEEE SC2003 Conference on High Performance Networking and Computing, 2003

A High Performance and Low Cost Cluster-Based E-mail System.
Proceedings of the Parallel Computing Technologies, 2003

A Case Study of System Level Specification and Software Synthesis of Multimode Multimedia Terminal.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

An Energy Optimization Technique for Latency and Quality Constrained Video Applications.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Schedule-aware performance estimation of communication architecture for efficient design space exploration.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Memory access pattern analysis and stream cache design for multimedia applications.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Combined data-driven and event-driven scheduling technique for fast distributed cosimulation.
IEEE Trans. VLSI Syst., 2002

An Efficient Implementation of the BSP Programming Library for VIA.
Parallel Processing Letters, 2002

Extended Synchronous Dataflow for Efficient DSP System Prototyping.
Design Autom. for Emb. Sys., 2002

Fractional rate dataflow model and efficient code synthesis for multimedia applications.
Proceedings of the 2002 Joint Conference on Languages, 2002

Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Efficient code synthesis from extended dataflow graphs for multimedia applications.
Proceedings of the 39th Design Automation Conference, 2002

Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Hybrid Run-time Power Management Technique for Real-time Embedded System with Voltage Scalable Processor.
Proceedings of The Workshop on Languages, 2001

Dynamic voltage scheduling technique for low-power multimedia applications using buffers.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

xBSP: An Efficient BSP Implementation for clan.
Proceedings of the First IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2001), 2001

A dataflow specification for system level synthesis of 3D graphics applications.
Proceedings of ASP-DAC 2001, 2001

2000
Memory efficient software synthesis with mixed coding style from dataflow graphs.
IEEE Trans. VLSI Syst., 2000

Hardware Synthesis from SPDF Representation for Multimedia Applications.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Data memory minimization by sharing large size buffers.
Proceedings of ASP-DAC 2000, 2000

1999
Extended Synchronous Dataflow for Efficient DSP System Prototyping.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing.
VLSI Design, 1998

Relaxed Barrier Synchronization for the BSP Model of Computation on Message-Passing Architectures.
Inf. Process. Lett., 1998

Memory Efficient Software Synthesis from Dataflow Graph.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Efficient Barrier Synchronization Mechanism for BSP Model on Message Passing Architectures.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

Optimized Timed Hardware Software Cosimulation without Roll-back.
Proceedings of the 1998 Design, 1998

Rate Optimal VLSI Design from Data Flow Graph.
Proceedings of the 35th Conference on Design Automation, 1998

A Hardware Software Cosimulation Backplane with Automatic Interface Generation.
Proceedings of the ASP-DAC '98, 1998

1997
Heterogeneous Simulation - Mixing Discrete-Event Models with Dataflow.
VLSI Signal Processing, 1997

Software synthesis for dynamic data flow graph.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

Reducing Overheads of Local Communications in Fine-grain Parallel Computation.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Quantitative Analysis on Caching Effect of I-Structure Data in Frame-Based Multithreaded Processing.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
COP: a Crosstalk OPtimizer for gridded channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

A Static Scheduling Heuristic for Heterogeneous Processors.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
Software synthesis for DSP using ptolemy.
VLSI Signal Processing, 1995

An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems.
Int. Journal in Computer Simulation, 1994

1991
Compile-Time Scheduling and Assignment of Data-Flow Program Graphs with Data-Dependent Iteration.
IEEE Trans. Computers, 1991


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