Soonhoi Ha
Orcid: 0000-0001-7472-9142Affiliations:
- Seoul National University, South Korea
- University of California at Berkeley, CA, USA (PhD)
According to our database1,
Soonhoi Ha
authored at least 197 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2017, "For contributions to hardware/software codesign".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on dl.acm.org
On csauthors.net:
Bibliography
2024
IEEE Des. Test, February, 2024
A Novel Throughput Enhancement Method for Deep Learning Applications on Mobile Devices With Heterogeneous Processors.
IEEE Access, 2024
2023
Internet Things, December, 2023
Energy-Aware Scenario-Based Mapping of Deep Learning Applications Onto Heterogeneous Processors Under Real-Time Constraints.
IEEE Trans. Computers, June, 2023
A Novel Technique to Support Deep Learning Applications in a Model-Based Embedded Software Design Methodology.
IEEE Access, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
TensorRT-Based Framework and Optimization Methodology for Deep Learning Inference on Jetson Boards.
ACM Trans. Embed. Comput. Syst., September, 2022
ACM Trans. Design Autom. Electr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Computers, 2022
IEEE Embed. Syst. Lett., 2022
IEEE Des. Test, 2022
Analysis of the Effect of Off-chip Memory Access on the Performance of an NPU System.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
Dataflow Model-based Software Synthesis Framework for Parallel and Distributed Embedded Systems.
ACM Trans. Design Autom. Electr. Syst., 2021
Des. Autom. Embed. Syst., 2021
IEEE Access, 2021
Fast Simulation of a Many-NPU Network-on-Chip for Microarchitectural Design Space Exploration.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
2020
Scheduling of Deep Learning Applications Onto Heterogeneous Processors in an Embedded Device.
IEEE Access, 2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Software Development Framework for Cooperating Robots with High-level Mission Specification.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020
Tensor Virtualization Technique to Support Efficient Data Reorganization for CNN Accelerators.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT Analysis.
ACM Trans. Design Autom. Electr. Syst., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
A Novel Convolutional Neural Network Accelerator That Enables Fully-Pipelined Execution of Layers.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Fast Performance Estimation and Design Space Exploration of Manycore-based Neural Processors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Real Time Syst., 2018
Fast parallel simulation of a manycore architecture with a flit-level on-chip network model.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Joint optimization of speed, accuracy, and energy for embedded image recognition systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
NNsim: fast performance estimation based on sampled simulation of GPGPU kernels for neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the Principles of Modeling, 2018
Service-Oriented Robot Software Development Framework for Distributed Heterogeneous Platforms.
Proceedings of the 17th International Conference on Autonomous Agents and MultiAgent Systems, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Multiprocessor Scheduling of a Multi-Mode Dataflow Graph Considering Mode Transition Delay.
ACM Trans. Design Autom. Electr. Syst., 2017
Worst-Case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-Time Tasks.
ACM Trans. Design Autom. Electr. Syst., 2017
Proceedings of the Seventh International Conference on the Internet of Things, 2017
Proceedings of the 2017 IEEE International Conference on Software Testing, 2017
Worst case delay analysis of shared resource access in partitioned multi-core systems.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017
Proceedings of the Thirteenth ACM International Conference on Embedded Software 2017 Companion, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017
Proceedings of the 2017 International Conference on Compilers, 2017
2016
A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Power Optimization of Multimode Mobile Embedded Systems with Workload-Delay Dependency.
Mob. Inf. Syst., 2016
SoPHy+: Programming model and software platform for hybrid resource management of many-core accelerators.
Microprocess. Microsystems, 2016
J. Syst. Archit., 2016
An Adaptive Frames Per Second-Based CPU-GPU Cooperative Dynamic Voltage and Frequency Scaling Governing Technique for Mobile Games.
J. Low Power Electron., 2016
Multiprocessor Scheduling of an SDF Graph with Library Tasks Considering the Worst Case Contention Delay.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016
Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IEEE Trans. Computers, 2015
Fast GPU-in-the-loop simulation technique at OpenGL ES API level for Android Graphics Applications.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015
Modeling and power optimization of cyber-physical systems with energy-workload tradeoff.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2014
Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems: HOPES Approach.
ACM Trans. Embed. Comput. Syst., 2014
System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation.
Microprocess. Microsystems, 2014
An efficient parallelization technique for x264 encoder on heterogeneous platforms consisting of CPUs and GPUs.
J. Real Time Image Process., 2014
SoPHy: A Software Platform for Hybrid Resource Management of Homogeneous Many-core Accelerators.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Software platform for hybrid resource management of a many-core accelerator for multimedia applications.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Decidable Dataflow Models for Signal Processing: Synchronous Dataflow and Its Extensions.
Proceedings of the Handbook of Signal Processing Systems, 2013
Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints.
J. Signal Process. Syst., 2013
Efficient run-time resource management of a manycore accelerator for stream-based applications.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013
A novel analytical method for worst case response time estimation of distributed embedded systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A parallel and distributed meta-heuristic framework based on partially ordered knowledge sharing.
J. Parallel Distributed Comput., 2012
Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC.
Des. Autom. Embed. Syst., 2012
An ILP-based Worst-case Performance Analysis Technique for Distributed Real-time Embedded Systems.
Proceedings of the 33rd IEEE Real-Time Systems Symposium, 2012
A cycle-level parallel simulation technique exploiting both space and time parallelism.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Multi-objective mapping optimization via problem decomposition for many-core systems.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching.
Proceedings of the Computing Frontiers Conference, CF'12, 2012
Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Ind. Informatics, 2011
Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Proceedings of the Parallel Processing and Applied Mathematics, 2011
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Simulation environment configuration for parallel simulation of multicore embedded systems.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification.
J. Signal Process. Syst., 2010
ACM Trans. Design Autom. Electr. Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
Decidable Signal Processing Dataflow Graphs: Synchronous and Cyclo-Static Dataflow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
J. Discrete Algorithms, 2009
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis.
J. Signal Process. Syst., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
ACM Trans. Embed. Comput. Syst., 2008
Parallel Comput., 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Automatic H.264 encoder synthesis for the Cell processor from a target independent specification.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Data-Parallel Code Generation from Synchronous Dataflow Specification of Multimedia Applications.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
CATS: cycle accurate transaction-driven simulation with multiple processor simulators.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems.
Proceedings of the 2007 International Conference on Compilers, 2007
Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006
Proceedings of the OpenMP Shared Memory Parallel Programming - International Workshops, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Schedule-aware performance estimation of communication architecture for efficient design space exploration.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the Embedded Software and Systems, Second International Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.
Proceedings of the 2005 International Conference on Compilers, 2005
Embedded software generation from system level specification for multi-tasking embedded systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
J. VLSI Signal Process., 2004
ACM Trans. Embed. Comput. Syst., 2004
IEEE Des. Test Comput., 2004
Proceedings of the 12th Euromicro Workshop on Parallel, 2004
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Fast design space exploration framework with an efficient performance estimation technique.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
2003
Memory-Optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples.
EURASIP J. Adv. Signal Process., 2003
Des. Autom. Embed. Syst., 2003
Design and implementation of a user-level Sockets layer over Virtual Interface Architecture.
Concurr. Comput. Pract. Exp., 2003
Proceedings of the ACM/IEEE SC2003 Conference on High Performance Networking and Computing, 2003
Proceedings of the Parallel Computing Technologies, 2003
A Case Study of System Level Specification and Software Synthesis of Multimode Multimedia Terminal.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
An Energy Optimization Technique for Latency and Quality Constrained Video Applications.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Combined data-driven and event-driven scheduling technique for fast distributed cosimulation.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Efficient hardware controller synthesis for synchronous dataflow graph in system level design.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Parallel Process. Lett., 2002
Des. Autom. Embed. Syst., 2002
Fractional rate dataflow model and efficient code synthesis for multimedia applications.
Proceedings of the 2002 Joint Conference on Languages, 2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Proceedings of the 39th Design Automation Conference, 2002
Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
2001
Hybrid Run-time Power Management Technique for Real-time Embedded System with Voltage Scalable Processor.
Proceedings of The Workshop on Languages, 2001
Dynamic voltage scheduling technique for low-power multimedia applications using buffers.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the First IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2001), 2001
Proceedings of ASP-DAC 2001, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Proceedings of the 13th International Symposium on System Synthesis, 2000
Proceedings of ASP-DAC 2000, 2000
1999
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999
1998
VLSI Design, 1998
Relaxed Barrier Synchronization for the BSP Model of Computation on Message-Passing Architectures.
Inf. Process. Lett., 1998
Proceedings of the 11th International Symposium on System Synthesis, 1998
Efficient Barrier Synchronization Mechanism for BSP Model on Message Passing Architectures.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998
Proceedings of the 1998 Design, 1998
Rate Optimal VLSI Design from Data Flow Graph.
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the ASP-DAC '98, 1998
1997
J. VLSI Signal Process., 1997
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997
Quantitative Analysis on Caching Effect of I-Structure Data in Frame-Based Multithreaded Processing.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996
1995
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems.
Int. J. Comput. Simul., 1994
1991
Compile-Time Scheduling and Assignment of Data-Flow Program Graphs with Data-Dependent Iteration.
IEEE Trans. Computers, 1991
Proceedings of the 1991 International Conference on Acoustics, 1991