James D. Trotter

Orcid: 0000-0003-4498-020X

According to our database1, James D. Trotter authored at least 11 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
ucTrace: A Multi-Layer Profiling Tool for UCX-driven Communication.
CoRR, February, 2026

Cache partitioning for sparse matrix-vector multiplication on the A64FX.
Parallel Comput., 2026

Performance and Programmability of MPI+X Integration with CUDA, HIP, SYCL, OpenACC, and OpenMP Offloading for Supercomputing: A Case Study on Dense Matrix-Vector Multiplication.
Proceedings of the Supercomputing Asia and International Conference on High Performance Computing in Asia Pacific Region Workshops, 2026

2025
CPU- and GPU-initiated Communication Strategies for Conjugate Gradient Methods on Large GPU Clusters.
Proceedings of the International Conference for High Performance Computing, 2025

Modelling Load Imbalance In Shared Memory Multicore Systems.
Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, 2025

2023
Targeting performance and user-friendliness: GPU-accelerated finite element computation with automated code generation in FEniCS.
Parallel Comput., November, 2023

Bringing Order to Sparsity: A Sparse Matrix Reordering Study on Multicore CPUs.
Proceedings of the International Conference for High Performance Computing, 2023

Modelling Data Locality of Sparse Matrix-Vector Multiplication on the A64FX.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Performance Prediction for Sparse Matrix Vector Multiplication Using Structure-Dependent Features.
Proceedings of the Euro-Par 2023: Parallel Processing Workshops - Euro-Par 2023 International Workshops, Limassol, Cyprus, August 28, 2023

2022
On Memory Traffic and Optimisations for Low-order Finite Element Assembly Algorithms on Multi-core CPUs.
ACM Trans. Math. Softw., 2022

2020
Cache simulation for irregular memory traffic on multi-core CPUs: Case study on performance models for sparse matrix-vector multiplication.
J. Parallel Distributed Comput., 2020


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