Jayanta Biswas

According to our database, Jayanta Biswas authored at least 5 papers between 2006 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2019

An optimized harmonic elimination method based on synchronizedmicrocontroller architecture.

Vivek Gopinath, Meenu Nair, Jayanta Biswas, Mukti Barai

Turkish J. Electr. Eng. Comput. Sci., 2019

2017

Study on hybrid SVPWM sequences for two level VSIs.

G. Vivek, Jayanta Biswas

Proceedings of the IEEE International Conference on Industrial Technology, 2017

2006

Efficient Key Management and Distribution for MANET.

Jayanta Biswas, Soumitra Kumar Nandy

Proceedings of IEEE International Conference on Communications, 2006

A Cost Effective Pipelined Divider for Double Precision Floating Point Number.

Sandeep B. Singh, Jayanta Biswas, S. K. Nandy

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

High Performance VLSI Architecture Design for H.264 CAVLC Decoder.

Mythri Alle, Jayanta Biswas, S. K. Nandy

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006