Mythri Alle

According to our database¹, Mythri Alle authored at least 18 papers between 2006 and 2013.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2013

GeCoS: A framework for prototyping custom hardware design flows.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, 2013

Runtime dependency analysis for loop pipelining in high-level synthesis.

[BibT_eX]

[DOI]

Mythri Alle

Antoine Morvan

Steven Derrien

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2011

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Compilers, 2010

2009

REDEFINE: Runtime reconfigurable polymorphic ASIC.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2009

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Compilers, 2009

An Input Triggered Polymorphic ASIC for H.264 Decoding.

[BibT_eX]

[DOI]

Sreeramula Sankaraiah

Sravanthi Mantha

S. K. Nandy

Ranjani Narayan

Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Synthesis of application accelerators on Runtime Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

2006

High Performance VLSI Architecture Design for H.264 CAVLC Decoder.

[BibT_eX]

[DOI]

Mythri Alle

Jayanta Biswas

S. K. Nandy

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Mythri Alle

Timeline

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