Jayashree Sridharan

According to our database, Jayashree Sridharan authored at least 5 papers between 2004 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis.

Jayashree Sridharan, Tom Chen

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Modeling multiple input switching of CMOS gates in DSM technology using HDMR.

Jayashree Sridharan, Tom Chen

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Mapping subtasks with multiple versions on an ad hoc grid.

Sameer Shivle, Prasanna Sugavanam, Howard Jay Siegel, Anthony A. Maciejewski, Tarun Banka, Kiran Chindam, Steve Dussinger, Andrew Kutruff, Prashanth Penumarthy, Prakash Pichumani, Praveen Satyasekaran, David Sendek, Jay Smith, J. Sousa, Jayashree Sridharan, Jose Velazco

Parallel Comput., 2005

2004

Mapping of Subtasks with Multiple Versions in a Heterogeneous Ad Hoc Grid Environment.

Sameer Shivle, Howard Jay Siegel, Anthony A. Maciejewski, Tarun Banka, Kiran Chindam, Steve Dussinger, Andrew Kutruff, Prashanth Penumarthy, Prakash Pichumani, Praveen Satyasekaran, David Sendek, J. Sousa, Jayashree Sridharan, Prasanna Sugavanam, Jose Velazco

Proceedings of the 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 2004

Static Mapping of Subtasks in a Heterogeneous Ad Hoc Grid Environment.

Sameer Shivle, Ralph H. Castain, Howard Jay Siegel, Anthony A. Maciejewski, Tarun Banka, Kiran Chindam, Steve Dussinger, Prakash Pichumani, Praveen Satyasekaran, William W. Saylor, David Sendek, J. Sousa, Jayashree Sridharan, Prasanna Sugavanam, Jose Velazco

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004