Je-Hoon Lee

Orcid: 0000-0001-9481-2891

According to our database1, Je-Hoon Lee authored at least 23 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Health to Eat: A Smart Plate with Food Recognition, Classification, and Weight Measurement for Type-2 Diabetic Mellitus Patients' Nutrition Control.
Sensors, February, 2023

2022
Cyber-Physical System Platform and Applications for Smart Manufacturing in Global Automotive Industry.
Proceedings of the Advances in Production Management Systems. Smart Manufacturing and Logistics Systems: Turning Ideas into Action, 2022

2021
Black-sun noise immune correlated double sampling scheme for CMOS image sensors.
IEICE Electron. Express, 2021

2016
Power Modeling Framework for an Asynchronous Processor.
J. Circuits Syst. Comput., 2016

2015
Design of <i>q</i>-Parallel LFSR-Based Syndrome Generator.
IEICE Trans. Electron., 2015

2014
Asynchronous Instruction Cache Memory for Average-Case Performance.
J. Circuits Syst. Comput., 2014

2011
Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design.
Microelectron. J., 2011

A Self-Timed SRAM Design for Average-Case Performance.
IEICE Trans. Inf. Syst., 2011

High-Speed FPGA Implementation of the SHA-1 Hash Function.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010
Performance and Power Modeling of On-Chip Bus System for a Complex SoC.
IEICE Trans. Electron., 2010

2009
A hybrid control scheme for driving current sources of pm-oled panel.
IEEE Trans. Consumer Electron., 2009

Cycle Time Synchronization Technique for IEEE 1394 over UWB Network.
IEICE Trans. Commun., 2009

Implementation of HIGHT cryptic circuit for RFID tag.
IEICE Electron. Express, 2009

Implementation of high-speed SHA-1 architecture.
IEICE Electron. Express, 2009

2008
A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Design of a high performance self-timed ARM9 processor.
IEICE Electron. Express, 2008

2007
Isochronous Data Transfer between AV Devices Using Pseudo CMP Protocol in IEEE 1394 over UWB Network.
IEICE Trans. Commun., 2007

On-Chip Bus Modeling for Power and Performance Estimation.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Composite Endoscope Images from Massive Inner Intestine Photos.
Proceedings of the New Trends in Applied Artificial Intelligence, 2007

Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme.
Proceedings of the Embedded Computer Systems: Architectures, 2006

New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006


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