Kyoung-Rok Cho

According to our database1, Kyoung-Rok Cho authored at least 69 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Nonlinear retinal response modeling for future neuromorphic instrumentation.
IEEE Instrum. Meas. Mag., 2020

2019
Performance analysis of structural similarity-based backlight dimming algorithm modulated by controlling allowable local distortion of output image.
Displays, 2019

Adaptive Precision CNN Accelerator Using Radix-X Parallel Connected Memristor Crossbars.
CoRR, 2019

Statistical Modeling of Read Static Noise Margin for 6-Transistor SRAM cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Memristor-CMOS Braun Multiplier Array for Arithmetic Pipelining.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Neuromorphic Vision Hybrid RRAM-CMOS Architecture.
IEEE Trans. VLSI Syst., 2018

High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic.
Microelectronics Journal, 2018

Implementation of real-time image edge detector based on a bump circuit and active pixels in a CMOS image sensor.
Integr., 2018

Formulation and Implementation of Nonlinear Integral Equations to Model Neural Dynamics Within the Vertebrate Retina.
Int. J. Neural Syst., 2018

Extract LUT Logics from a Downloaded Bitstream Data in FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Maximization of Crossbar Array Memory Using Fundamental Memristor Theory.
IEEE Trans. on Circuits and Systems, 2017

Biological modeling of vertebrate retina: Rod cell to bipolar cell.
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017

Touched image transmission of a high resolution touch panel using MIPI CSI-2 for kiosk applications.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017

2016
Modelling and analysis of signal flow platform implementation into retinal cell pathway.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Live demonstration: Signal flow platform implementation into retinal cell pathway.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Memristor-CMOS logic and digital computational components.
Microelectronics Journal, 2015

Design of q-Parallel LFSR-Based Syndrome Generator.
IEICE Transactions, 2015

Automatic depth map generation from a single image using segment-adaptive depth merging.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

2014
High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture.
IEEE Trans. VLSI Syst., 2014

2013
Complementary Resistive Switch (CRS) based smart sensor search engine.
Proceedings of the 2013 IEEE Eighth International Conference on Intelligent Sensors, 2013

Two-stage charge sensing circuit for a mutual-capacitive touch screen panel.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2012
Memristive Device Fundamentals and Modeling: Applications to Circuits and Systems Simulation.
Proceedings of the IEEE, 2012

Design of D-PHY chip for mobile display interface supporting MIPI standard.
Microelectronics Journal, 2012

Tunable continuous-time ΔΣ modulator for switching power amplifier.
IEICE Electronic Express, 2012

Live demonstration: High fill factor CIS based on single inverter architecture.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Uncompressed video transmission in portable devices for wireless video mirroring service.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012

Design of a D-PHY chip for mobile display interface supporting MIPI standard.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012

2011
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines.
IEEE Trans. VLSI Syst., 2011

Gigabit UWB video transmission system for wireless video area network.
IEEE Trans. Consumer Electronics, 2011

Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design.
Microelectronics Journal, 2011

Memristor-based Synaptic Networks and Logical Operations Using In-Situ Computing
CoRR, 2011

An Analytical Approach for Memristive Nanoarchitectures
CoRR, 2011

2010
3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications.
IEEE Trans. Biomed. Circuits and Systems, 2010

Performance and Power Modeling of On-Chip Bus System for a Complex SoC.
IEICE Transactions, 2010

Performance analysis of random access in IEEE 802.16m system.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2010

2009
A hybrid control scheme for driving current sources of pm-oled panel.
IEEE Trans. Consumer Electronics, 2009

Implementation of HIGHT cryptic circuit for RFID tag.
IEICE Electronic Express, 2009

Implementation of high-speed SHA-1 architecture.
IEICE Electronic Express, 2009

System-on-System (SoS) architecture for 3-D secure imaging.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure.
IEEE Trans. on Circuits and Systems, 2008

Priority-based dynamic bandwidth allocation in Ethernet Passive Optical Networks.
Photonic Network Communications, 2008

Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's.
IEICE Transactions, 2008

Design of a high performance self-timed ARM9 processor.
IEICE Electronic Express, 2008

2007
Motion Compensated Frame Rate Up-Conversion Using Extended Bilateral Motion Estimation.
IEEE Trans. Consumer Electronics, 2007

Improvement of Sleep Operation for the Reduced Paging Delay on Cellular System.
IEICE Transactions, 2007

On-Chip Bus Modeling for Power and Performance Estimation.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Processing Acceleration of Broadband Wireless MAC in a Portable Terminal.
IEICE Transactions, 2006

A Hybrid Decimal Division Algorithm Reducing Computational Iterations.
IEICE Transactions, 2006

Modeling and analysis of the system bus latency on the SoC platform.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme.
Proceedings of the Embedded Computer Systems: Architectures, 2006

New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005
A novel CMOS operational transconductance amplifier based on a mobility compensation technique.
IEEE Trans. on Circuits and Systems, 2005

Performance Analysis of Symbol Error Probability for MPSK with an I-Q Unbalance over a Rician Fading Channel.
IEICE Transactions, 2005

A DSP-Based Reconfigurable SDR Platform for 3G Systems.
IEICE Transactions, 2005

Mobile Tracking Using Fuzzy Multi-criteria Decision Making.
Proceedings of the Mobile Ad-hoc and Sensor Networks, First International Conference, 2005

A Study on the Enhanced Detection Method Considering the Channel Response in OFDM Based WLAN.
Proceedings of the Advances in Intelligent Computing, 2005

Performance Evaluation of Convolutional Turbo Codes in AWGN and ITU-R Channels.
Proceedings of the Advances in Intelligent Computing, 2005

Convolutional Turbo Coded OFDM/TDD Mobile Communication System for High Speed Multimedia Services.
Proceedings of the Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 2005

2004
Design and Evaluation of Redundant IPC Network Adequate for an Edge Router.
Proceedings of the First International Workshop, 2004

Design of a New IFFT/FFT for IEEE 802.11a WLAN Based on the Statistics Distribution of the Input Data.
Proceedings of the High Speed Networks and Multimedia Communications, 2004

2003
Traffic control schemes and performance analysis of multimedia service in cellular systems.
IEEE Trans. Vehicular Technology, 2003

A real-time voice service with the adaptive packet loss recovery scheme in the hybrid residential gateway system.
IEEE Trans. Consumer Electronics, 2003

Turbo-Coded OFDM/TDMA System for Beyond 3G Mobile Multimedia Communications.
Proceedings of the International Conference on Wireless Networks, 2003

2002
Design of HG-iPhone Service Based on H.323 in the Home Gateway System.
Proceedings of the Information Networking, 2002

2001
Backward Propagated Capacitance Model for Register Transfer Level Power Estimation.
VLSI Design, 2001

2000
Optimum reserved resource allocation scheme for handoff in CDMA cellular system.
Journal of Systems Architecture, 2000

Traffic Model for the Channel Assignment Scheme Based on Cell Partitioning in CDMA Mobile Systems.
Proceedings of the 2000 IEEE International Conference on Communications: Global Convergence Through Communications, 2000


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