Jeevan Sirkunan

According to our database1, Jeevan Sirkunan authored at least 6 papers between 2014 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Bufferless network traffic classification using reinforcement learning-based joint pruning-quantization.
Evol. Intell., February, 2026

2024
Correlation-Aware Joint Pruning-Quantization using Graph Neural Networks.
Proceedings of the IEEE International Conference on Image Processing, 2024

2019
Interleaved Incremental/Decremental Support Vector Machine for Embedded System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017
Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms.
J. Syst. Archit., 2017

2015
Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Hardware transactional memory on multi-processor FPGA platform.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014


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