Jeevan Sirkunan

According to our database, Jeevan Sirkunan authored at least 4 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Interleaved Incremental/Decremental Support Vector Machine for Embedded System.

Jeevan Sirkunan, Nasir Shaikh-Husin, Muhammad N. Marsono

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017

Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms.

Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono

J. Syst. Archit., 2017

2015

Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms.

Jeevan Sirkunan, Chia Yee Ooi, Muhammad N. Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

Hardware transactional memory on multi-processor FPGA platform.

Jeevan Sirkunan, Chia Yee Ooi, Nasir Shaikh-Husin, Yuan Wen Hau, Muhammad Nadzir Marsono

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014