Jeongwoo Park
Orcid: 0000-0002-9603-9588Affiliations:
- Sungkyunkwan University, Electrical and Computer Engineering Department, Suwon, South Korea
- Seoul National University, Department of Electrical and Computer Engineering, Seoul, South Korea (PhD 2022)
According to our database1,
Jeongwoo Park authored at least 16 papers
between 2019 and 2026.
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Bibliography
2026
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026
BOA-3DGS: Backward-Striding Optimized Accelerator for Reduced Memory Contention in 3D Gaussian Splatting Training.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026
2025
CLAT: A Clustering-Based Attention Transformer Accelerator for Low-Latency Text Generation in LLMs.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
IEEE J. Solid State Circuits, May, 2025
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
Proceedings of the 21st International SoC Design Conference, 2024
2023
A0.81 mm<sup>2</sup> 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees.
IEEE J. Solid State Circuits, 2022
Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization.
Proceedings of the Tenth International Conference on Learning Representations, 2022
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Activation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback.
IEEE J. Solid State Circuits, 2020
2019
A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019