Ji-Ping Na

According to our database, Ji-Ping Na authored at least 3 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR.

Bing Li, Ji-Ping Na, Wei Wang, Jia Liu, Qian Yang, Pui-In Mak

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

A 480 fJ/conversion-step 13-bit Resistive Sensor Readout IC with a 1%/V Power Supply Sensitivity.

Bing Li, Ji-Ping Na, Wei Wang, Jia Liu, Wen-Jun Liu, Qian Yang, Wen Bin Ye

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A high-sensitivity signal conditioning interface for capacitive touch key using ΔΣ modulation.

Bing Li, Lin-Fa Ma, Wei Wang, Ji-Ping Na, Chuang Li

Proceedings of the International SoC Design Conference, 2017