Bing Li
Orcid: 0000-0002-8951-6112Affiliations:
- Shenzhen University, College of Electronic Science and Technology, China
- Chinese University of Hong Kong, Hong Kong (PhD 2013)
According to our database1,
Bing Li authored at least 18 papers
between 2009 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2026
A 1.69$\mu$J Highly Robust Cardiac Arrhythmia Monitoring Processor With Triple-Adaptive QRS Detector and Medically Driven Feature-Fusion Hybrid Neural Networks.
IEEE Trans. Biomed. Circuits Syst., June, 2026
A Sampling-Settling-Merged Technique Enabling an ELDC-Free Continuous-Time Delta-Sigma Modulator With a Pole-Optimized NS-SAR Quantizer.
IEEE Trans. Very Large Scale Integr. Syst., February, 2026
2025
A 900-nW Wearable Interpatient Cardiac Arrhythmia Monitoring Processor With a Feature Engine-Based Artificial Neural Network.
IEEE Internet Things J., July, 2025
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025
2024
A 1.83 μ J High-Robust Cardiac Health Monitoring with Adaptive-Threshold QRS Detector and Hybrid Neural Network Arrhythmia Classifier.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024
2023
An 842 nW Wearable Inter-Patient Cardiac Arrhythmia Monitoring Processor with a Feature Engine-Based Artificial Neural Network.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
A 23.5 μA Ultra-Low Standby Power Microphone ASIC with the Voice Activity Detection Based on A Level-Crossing ADC.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2019
A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
A 1 pF-to-10 nF Generic Capacitance-to-Digital Converter Using Zero-Crossing ΔΣ Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 480 fJ/conversion-step 13-bit Resistive Sensor Readout IC with a 1%/V Power Supply Sensitivity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Energy-Efficient 13-bit Zero-Crossing ΔΣ Capacitance-to-Digital Converter with 1 pF-to-10 nF Sensing Range.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
A high-sensitivity signal conditioning interface for capacitive touch key using ΔΣ modulation.
Proceedings of the International SoC Design Conference, 2017
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2014
A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
A continuous-time cascaded delta-sigma modulator with PMW-based automatic RC time constant tuning and correlated double sampling.
Microelectron. J., 2013
2009
A Novel Mismatch Cancellation and I/Q Channel Multiplexing Scheme for Quadrature Bandpass DeltaSigma Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009