Pui-In Mak
Orcid: 0000-0002-3579-8740
According to our database1,
Pui-In Mak
authored at least 292 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter With Relieved Capacitor Inrush Current and C<sub>OUT</sub>-Free Operations.
IEEE J. Solid State Circuits, April, 2024
A 1024-Channel 268-nW/Pixel 36×36 μm<sup>2</sup>/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.
IEEE J. Solid State Circuits, April, 2024
Extended Power Dynamic Range and Enhanced Power Conversion Efficiency of a Switched-Capacitor DC-DC Converter: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
A 0.05-mm<sup>2</sup> 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS.
IEEE J. Solid State Circuits, February, 2024
A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time.
IEEE J. Solid State Circuits, February, 2024
One-Cycle-Startup Relaxation Oscillator Using Ratiometric Threshold-Referenced and Self-Synchronized Power Gating Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
A Constant-Power and Optimal-Transfer-Efficiency Wireless Inductive Power Transfer Converter for Battery Charger.
IEEE Trans. Ind. Electron., 2024
19.4 A 0.07 mm<sup>2</sup> 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10 MHz and 200.7dBc/Hz FoMA in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
23.4 A 167 μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
7.4 A 0.027mm<sup>2</sup> 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
17.2 A Miniature Multi-Nuclei NMR/MRI Platform with a High-Voltage SOI ASIC Achieving a 134.4dB Image SNR with a 173×250×103μm<sup>3</sup> Resolution.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced I<sub>L</sub> Reduction for 12 V/24 V Inputs.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM.
IEEE J. Solid State Circuits, November, 2023
A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A 0.4-V 8400-μm<sup>2</sup> Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
A 0.4-V 0.0294-mm<sup>2</sup> Resistor-Based Temperature Sensor Achieving ±0.24 °C p2p Inaccuracy From40 °C to 125 °C and 385 fJ · K<sup>2</sup> Resolution FoM in 65-nm CMOS.
IEEE J. Solid State Circuits, September, 2023
Modeling-Attack-Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability.
IEEE Internet Things J., September, 2023
A 0.0043-mm<sup>2</sup> 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation.
Int. J. Circuit Theory Appl., May, 2023
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
A 3.78-GHz Type-I Sampling PLL With a Fully Passive K<sub>PD</sub>-Doubled Primary-Secondary S-PD Measuring 39.6-fs<sub>RMS</sub> Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO With a 200-kHz 1/f³ Phase Noise Corner.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fs<sub>RMS</sub>Jitter, -258.7-dB FOM, and -75.17-dBc Reference Spur.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With200 Million Training CRPs.
IEEE Trans. Inf. Forensics Secur., 2023
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
IEEE Trans. Circuits Syst. II Express Briefs, 2023
A 27-dBm, 0.92-GHz CMOS Power Amplifier With Mode Switching and a High-Q Compact Inductor (HQCI) Achieving a 30% Back-Off PAE.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS.
IEEE Open J. Circuits Syst., 2023
A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm<sup>3</sup> Field of View.
IEEE J. Solid State Circuits, 2023
A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application.
IEEE Access, 2023
A Fully-Integrated CMOS Dual-Band RF Energy Harvesting Front-End Employing Adaptive Frequency Selection.
IEEE Access, 2023
High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review.
IEEE Access, 2023
Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review.
IEEE Access, 2023
A Flexible Rooftop Photovoltaic-Inductive Wireless Power Transfer System for Low-Voltage DC Grid.
IEEE Access, 2023
A 0.05-to-3.1A 585mA/mm<sup>3</sup> 97.3%-Efficiency Outphase Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 1024-Channel 268 nW/pixel 36x36 μm<sup>2</sup>/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0nJ Startup Energy and 45.8μs Startup Time.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $\text{FoM}_{\mathrm{T}}$.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2<sup>nd</sup>-Harmonic Output.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Simple-Logic Comparator-Offset Mitigation Technique for Resistor-Based Temperature Sensor in DFLL.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Fully Integrated Reconfigurable Solar Energy Harvester for $100\mu\mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm<sup>2</sup>.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 0.5-to-1.5GHz BW-Extended Gain-Boosted N-Path Filter Using a Switched $\mathbf{g}_{\mathbf{m}}-\mathbf{C}$ Network Achieving 50MHz BW and 18.2dBm OB-IIP3.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A Cross-Coupled Hybrid SC Converter with Extended VCR Range and Intrinsic Loss Balance Achieving 90% Average Efficiency with 1.5% Variation Over Full Li-ion Battery Input Range and 0.95A/mm<sup>2</sup> Peak Current Density.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm<sup>2</sup> FoM for RF-Based Hybrid Energy Harvesting.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 0.1-V V<sub>IN</sub> Subthreshold 3-Stage Dual-Branch Charge Pump With 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 6-to-7.5-GHz 54-fs<sub>rms</sub> Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Low-Power Multiband Blocker-Tolerant Receiver With a Steep Filtering Slope Using an N-Path LNA With Feedforward OB Blocker Cancellation and Filtering-by-Aliasing Baseband Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Miniaturization of a Nuclear Magnetic Resonance System: Architecture and Design Considerations of Transceiver Integrated Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Sensors, 2022
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 0.0285-mm<sup>2</sup> 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 1.7-3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP₃ and 3.4-4.8 dB NF.
IEEE J. Solid State Circuits, 2022
A 266-μW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77-dB SFDR and -3-dBm OOB-B<sub>-1 dB</sub>.
IEEE J. Solid State Circuits, 2022
Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery.
IEEE J. Solid State Circuits, 2022
A 108-nW 0.8-mm<sup>2</sup> Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes - Fundamentals and Design Techniques.
IEEE Access, 2022
Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview.
IEEE Access, 2022
IEEE Access, 2022
Modelling and Analysis of ΔΣ-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Design Challenges and Considerations of Non-isolated Gate Driver for GaN-based Converters.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 108nW 0.8mm<sup>2</sup> Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Switched-Capacitor Hybrid Quadratic Buck Converter for 48V-Input Wide-Range Conversion.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor Technique.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 32dBm OOB-IIP3 BW-Extended 5G-NR Receiver with 4<sup>th</sup>-Order Gain-Boosted N-Path LNA.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Adaptive Line-Transient Enhancement Techniques for Dual-Path Hybrid Converter Achieving Ultra-Low Output Overshoot/Undershoot.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier For Multiband Uplink Radio Transceivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Wide-PCE-Dynamic-Range CMOS Cross-Coupled Differential-Drive Rectifier for Ambient RF Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 0.003-mm<sup>2</sup> 440fs<sub>RMS</sub>-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A High-Efficiency Dual-Antenna RF Energy Harvesting System Using Full-Energy Extraction With Improved Input Power Response.
IEEE Open J. Circuits Syst., 2021
A 0.35-V 5, 200-μm<sup>2</sup> 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator.
IEEE J. Solid State Circuits, 2021
Int. J. Circuit Theory Appl., 2021
A 12V-to-1V switched-capacitor-assisted hybrid converter with dual-path charge conduction and zero-voltage switching.
IEICE Electron. Express, 2021
A multi-path switched-capacitor-inductor hybrid DC-DC converter with reduced inductor loss and extended voltage conversion range.
IEICE Electron. Express, 2021
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique.
IEEE Access, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f<sup>3</sup> PN Corner Without Harmonic Tuning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 0.45-V 3.3-µW Resistor-Based Temperature Sensor Achieving 10mK Resolution in 65-nm CMOS.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement.
Proceedings of the 47th ESSCIRC 2021, 2021
Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error Rate.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2<sup>nd</sup>-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Cost-Effective Compensation Design for Output Customization and Efficiency Optimization in Series/Series-Parallel Inductive Power Transfer Converter.
IEEE Trans. Ind. Electron., 2020
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools.
IEEE Trans. Circuits Syst., 2020
A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM.
IEEE Trans. Circuits Syst., 2020
A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA.
IEEE J. Solid State Circuits, 2020
A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver.
IEEE J. Solid State Circuits, 2020
Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation.
IEEE J. Solid State Circuits, 2020
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.
IEEE Access, 2020
A 0.024-mm<sup>2</sup> 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3<sup>rd</sup>-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 6.4pJ/Bit Strong Physical Unclonable Function Based on Multiple-Stage Amplifier Chain.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Low Complexity Illumination-Invariant Motion Vector Detection Based on Logarithmic Edge Detection and Edge Difference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Unity-Power-Factor Inductive Power Transfer Converter with Inherent CC-to-CV Transition Ability for Automated Guided Vehicle Charging.
Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020
A 0.0285mm<sup>2</sup> 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 0.0018-mm<sup>2</sup> 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-g<sub>m</sub> Cell.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.044-mm<sup>2</sup> 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
CMOS Cross-Coupled Differential-Drive Rectifier in Subthreshold Operation for Ambient RF Energy Harvesting - Model and Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.0071-mm<sup>2</sup> 10.8ps<sub>pp</sub>-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 0.0056-mm<sup>2</sup> -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs.
IEEE J. Solid State Circuits, 2019
Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter With Wide Input Voltage Range and Enhanced Power Density.
IEEE J. Solid State Circuits, 2019
A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA.
Integr., 2019
Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm.
Proceedings of the 16th International Conference on Synthesis, 2019
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.003-mm<sup>2</sup> 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 0.032-mm<sup>2</sup> 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018
A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA.
IEEE J. Solid State Circuits, 2018
Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor.
IEEE J. Solid State Circuits, 2018
An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances.
IEEE J. Solid State Circuits, 2018
A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator With 14.2-nJ Startup Energy and 31.8-µW Steady-State Power.
IEEE J. Solid State Circuits, 2018
Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters.
IEEE J. Solid State Circuits, 2018
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2018
Overview of Recent Development on Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Guest Editorial Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications.
Proceedings of the 15th International Conference on Synthesis, 2018
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.0056mm<sup>2</sup> all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An inverse-class-F CMOS VCO with intrinsic-high-Q 1<sup>st</sup>- and 2<sup>nd</sup>-harmonic resonances for 1/f<sup>2</sup>-to-1/f<sup>3</sup> phase-noise suppression achieving 196.2dBc/Hz FOM.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state power.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm<sup>2</sup>.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °C for Wearable and Sensing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 73.9%-Efficiency CMOS Rectifier Using a Lower DC Feeding (LDCF) Self-Body-Biasing Technique for Far-Field RF Energy-Harvesting Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation.
IEEE Trans. Biomed. Eng., 2017
A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE J. Solid State Circuits, 2017
A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) P<sub>out</sub>.
IEEE J. Solid State Circuits, 2017
A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays.
IEEE J. Solid State Circuits, 2017
Fully Integrated Inductor-Less Flipping-Capacitor Rectifier for Piezoelectric Energy Harvesting.
IEEE J. Solid State Circuits, 2017
24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
22.2 A 1.7mm<sup>2</sup> inductorless fully integrated flipping-capacitor rectifier (FCR) for piezoelectric energy harvesting with 483% power-extraction enhancement.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A 0.4V 4.8μW 16MHz CMOS crystal oscillator achieving 74-fold startup-time reduction using momentary detuning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A Time-Interleaved Ring-VCO with Reduced 1/f<sup>3</sup> Phase Noise Corner, Extended Tuning Range and Inherent Divided Output.
IEEE J. Solid State Circuits, 2016
A µNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration With a Digital Microfluidic Device Inside a Portable Magnet.
IEEE J. Solid State Circuits, 2016
Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell.
J. Circuits Syst. Comput., 2016
ProtPOS: a python package for the prediction of protein preferred orientation on a surface.
Bioinform., 2016
2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 0.0045-mm<sup>2</sup> 32.4-µW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 0.02 mm<sup>2</sup> 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad.
IEEE J. Solid State Circuits, 2015
Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate.
IEEE J. Solid State Circuits, 2015
Corrections to "A 0.02 mm<sup>2</sup> 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad".
IEEE J. Solid State Circuits, 2015
A 3.6-mW 6-GHz current-reuse VCO-buffer with improved load drivability in 65-nm CMOS.
Int. J. Circuit Theory Appl., 2015
2.4 A 0.028mm<sup>2</sup> 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Predicting favorable protein docking poses on a solid surface by particle swarm optimization.
Proceedings of the IEEE Congress on Evolutionary Computation, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications.
IEEE J. Solid State Circuits, 2014
An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF.
IEEE J. Solid State Circuits, 2014
A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS.
IEEE J. Solid State Circuits, 2014
Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability.
Int. J. Circuit Theory Appl., 2014
Muscle and electrode motion artifacts reduction in ECG using adaptive Fourier decomposition.
Proceedings of the 2014 IEEE International Conference on Systems, Man, and Cybernetics, 2014
17.2 A 0.0013mm<sup>2</sup> 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
9.4 A 0.5V 1.15mW 0.2mm<sup>2</sup> Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Micropower two-stage amplifier employing recycling current-buffer Miller compensation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Design considerations of a low-noise receiver front-end and its spiral coil for portable NMR screening.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm<sup>2</sup> Die Size in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm<sup>2</sup> Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
15-nW Biopotential LPFs in 0.35-µm CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation.
IEEE Trans. Biomed. Circuits Syst., 2013
Correction to "A 0.016 mm<sup>2</sup> 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW".
IEEE J. Solid State Circuits, 2013
A 0.016-mm<sup>2</sup> 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW.
IEEE J. Solid State Circuits, 2013
A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013
A 1.7mW 0.22mm<sup>2</sup> 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Canonical Correlation Analysis Neural Network for Steady-State Visual Evoked Potentials Based Brain-Computer Interfaces.
Proceedings of the Advances in Neural Networks - ISNN 2013, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 0.5V 10GHz 8-phase LC-VCO Combining current-reuse and back-gate-coupling techniques consuming 2mW.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Sub-threshold standard cell library design for ultra-low power biomedical applications.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
2012
A 0.83-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35-µm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2012
Comput. Electr. Eng., 2012
Proceedings of the 2012 IEEE International Conference on Virtual Environments Human-Computer Interfaces and Measurement Systems, 2012
Proceedings of the 2012 IEEE International Conference on Virtual Environments Human-Computer Interfaces and Measurement Systems, 2012
A 0.016mm<sup>2</sup> 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Object Recognition Test in Peripheral Vision: A Study on the Influence of Object Color, Pattern and Shape.
Proceedings of the Brain Informatics - International Conference, 2012
A 0.8 µW 8-bit 1.5∼20-pF-input-range capacitance-to-digital converter for lab-on-chip digital microfluidics systems.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A 0.46-mm <sup>2</sup> 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS.
IEEE J. Solid State Circuits, 2011
Robust Learning of Mixture Models and Its Application on Trial Pruning for EEG Signal Analysis.
Proceedings of the New Frontiers in Applied Data Mining, 2011
A 0.46mm<sup>2</sup> 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A Solution to harmonic frequency problem: Frequency and phase coding-based brain-computer interface.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Proceedings of EUROCON 2011, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
2010
Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A 90nm CMOS Bio-potential Signal Readout Front-end with Improved Powerline Interference Rejection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers.
IET Circuits Devices Syst., 2007
A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A frequency up-conversion and two-step channel selection embedded CMOS D/A interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003