Jian Chen

Affiliations:
  • Intel Corporation, Hillsboro, OR, USA
  • University of Texas at Austin, Department of Computer Science and Engineering, TX, USA (PhD 2011)


According to our database1, Jian Chen authored at least 12 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Mechanistic Modeling of Architectural Vulnerability Factor.
ACM Trans. Comput. Syst., 2015

2014
Predictive Heterogeneity-Aware Application Scheduling for Chip Multiprocessors.
IEEE Trans. Computers, 2014

2011
Modeling program resource demand using inherent program characteristics.
Proceedings of the SIGMETRICS 2011, 2011

Autocorrelation analysis: a new and improved method for measuring branch predictability.
Proceedings of the SIGMETRICS 2011, 2011

Autocorrelation analysis: A new and improved method for branch predictability characterization.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

Predictive coordination of multiple on-chip resources for chip multiprocessors.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

2010
CantorSim: Simplifying Acceleration of Micro-architecture Simulations.
Proceedings of the MASCOTS 2010, 2010

A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009
TSS: Applying two-stage sampling in micro-architecture simulations.
Proceedings of the 17th Annual Meeting of the IEEE/ACM International Symposium on Modelling, 2009

Efficient program scheduling for heterogeneous multi-core processors.
Proceedings of the 46th Design Automation Conference, 2009

2008
Energy-aware application scheduling on a heterogeneous multi-core system.
Proceedings of the 4th International Symposium on Workload Characterization (IISWC 2008), 2008

2007
Hardware Efficient Piecewise Linear Branch Predictor.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007


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