Stijn Eyerman

Orcid: 0000-0002-2587-7541

According to our database1, Stijn Eyerman authored at least 67 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Accurate and Scalable Many-Node Simulation.
CoRR, 2024

Message from the Program Chairs; ISPASS 2024.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024

2023
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor.
IEEE Micro, 2023

Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022
Execution Time Estimation of Multithreaded Programs With Critical Sections.
IEEE Trans. Parallel Distributed Syst., 2022

Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study.
CoRR, 2022

Scale-Model Architectural Simulation.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021
Automatic Sublining for Efficient Sparse Memory Accesses.
ACM Trans. Archit. Code Optim., 2021

Scale-Model Simulation.
IEEE Comput. Archit. Lett., 2021

RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors.
IEEE Comput. Archit. Lett., 2021

Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model.
IEEE Comput. Archit. Lett., 2021

Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
PIUMA: Programmable Integrated Unified Memory Architecture.
CoRR, 2020

Breaking In-Order Branch Miss Recovery.
IEEE Comput. Archit. Lett., 2020

Projecting Performance for PIUMA using Down-Scaled Simulation.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2018
Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors.
IEEE Trans. Computers, 2018

Multi-Stage CPI Stacks.
IEEE Comput. Archit. Lett., 2018

Many-core graph workload analysis.
Proceedings of the International Conference for High Performance Computing, 2018

Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
Improving IBM POWER8 Performance Through Symbiotic Job Scheduling.
IEEE Trans. Parallel Distributed Syst., 2017

Linear Branch Entropy: Characterizing and Optimizing Branch Behavior in a Micro-Architecture Independent Way.
IEEE Trans. Computers, 2017

Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores.
IEEE Comput. Archit. Lett., 2017

Analyzing the scalability of managed language applications with speedup stacks.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Reliability-Aware Scheduling on Heterogeneous Multicore Processors.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics.
IEEE Trans. Computers, 2016

Maximizing Heterogeneous Processor Performance Under Power Constraints.
ACM Trans. Archit. Code Optim., 2016

Symbiotic job scheduling on the IBM POWER8.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Mechanistic Modeling of Architectural Vulnerability Factor.
ACM Trans. Comput. Syst., 2015

Micro-architecture independent analytical processor performance and power modeling.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Micro-architecture independent branch behavior characterization.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Revisiting symbiotic job scheduling.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2014
Multiprogram Throughput Metrics: A Systematic Approach.
ACM Trans. Archit. Code Optim., 2014

An Evaluation of High-Level Mechanistic Core Models.
ACM Trans. Archit. Code Optim., 2014

Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance.
ACM Trans. Archit. Code Optim., 2014

Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance.
IEEE Comput. Archit. Lett., 2014

The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Per-thread cycle accounting in multicore processors.
ACM Trans. Archit. Code Optim., 2013

Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications.
Proceedings of the 2013 ACM SIGPLAN International Conference on Object Oriented Programming Systems Languages & Applications, 2013

Criticality stacks: identifying critical threads in parallel programs using synchronization behavior.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
Probabilistic modeling for job symbiosis scheduling on SMT processors.
ACM Trans. Archit. Code Optim., 2012

Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

A mechanistic performance model for superscalar in-order processors.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

A first-order mechanistic model for architectural vulnerability factor.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

An efficient CPI stack counter architecture for superscalar processors.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Fine-grained DVFS using on-chip regulators.
ACM Trans. Archit. Code Optim., 2011

How sensitive is processor customization to the workload's input datasets?
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

2010
A Counter Architecture for Online DVFS Profitability Estimation.
IEEE Trans. Computers, 2010

Per-Thread Cycle Accounting.
IEEE Micro, 2010

Modeling critical sections in Amdahl's law and its implications for multicore design.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Interval simulation: Raising the level of abstraction in architectural simulation.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Probabilistic job symbiosis modeling for SMT processor scheduling.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
A mechanistic performance model for superscalar out-of-order processors.
ACM Trans. Comput. Syst., 2009

Memory-level parallelism aware fetch policies for simultaneous multithreading processors.
ACM Trans. Archit. Code Optim., 2009

MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

Per-thread cycle accounting in SMT processors.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008
System-Level Performance Metrics for Multiprogram Workloads.
IEEE Micro, 2008

Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

2007
A Top-Down Approach to Architecting CPI Component Performance Counters.
IEEE Micro, 2007

A Memory-Level Parallelism Aware Fetch Policy for SMT Processors.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

Studying Compiler-Microarchitecture Interactions through Interval Analysis.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Characterizing the branch misprediction penalty.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Efficient design space exploration of high performance embedded out-of-order processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A performance counter architecture for computing accurate CPI components.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006


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