Jeffrey Stuecheli

According to our database1, Jeffrey Stuecheli authored at least 22 papers between 2002 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
IBM's POWER10 Processor.
IEEE Micro, 2021



2019
IBM's Next Generation POWER Processor.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

2018
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI.
IBM J. Res. Dev., 2018

IBM POWER9 memory architectures for optimized systems.
IBM J. Res. Dev., 2018

2016
An Early Performance Study of Large-Scale POWER8 SMP Systems.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

2015
CAPI: A Coherent Accelerator Processor Interface.
IBM J. Res. Dev., 2015

The cache and memory subsystems of the IBM POWER8 processor.
IBM J. Res. Dev., 2015

Advanced features in IBM POWER8 systems.
IBM J. Res. Dev., 2015

2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

POWER8.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2011
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue.
IEEE Micro, 2011

Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

The virtual write queue: coordinating DRAM and last-level cache policies.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009
Bank-aware Dynamic Cache Partitioning for Multicore Architectures.
Proceedings of the ICPP 2009, 2009

2006
Automatic testcase synthesis and performance model validation for high performance PowerPC processors.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006

2002
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.
IBM J. Res. Dev., 2002


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