Jeffrey Stuecheli
According to our database1,
Jeffrey Stuecheli
authored at least 22 papers
between 2002 and 2021.
Collaborative distances:
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Bibliography
2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the EuroSys '21: Sixteenth European Conference on Computer Systems, 2021
2019
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019
2018
IBM J. Res. Dev., 2018
2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016
2015
2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
2011
IEEE Micro, 2011
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
2009
Proceedings of the ICPP 2009, 2009
2006
Automatic testcase synthesis and performance model validation for high performance PowerPC processors.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006
2002
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.
IBM J. Res. Dev., 2002