Jiangjiang Liu

Orcid: 0009-0006-1044-0423

Affiliations:
  • Lamar University, Beaumont, TX, USA


According to our database1, Jiangjiang Liu authored at least 32 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
A Survey on Deep Learning-based Smart Assistive Aids for Visually Impaired Individuals.
Proceedings of the 7th International Conference on Information System and Data Mining, 2023

Computer Science (CS) Day for Middle School Students.
Proceedings of the IEEE Frontiers in Education Conference, 2023

2019
Face Recognition Using Segmentation Technology.
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019

Mining Frequent Itemsets Using Improved Apriori on Spark.
Proceedings of the 3rd International Conference on Information System and Data Mining, 2019

2017
A Student Information Management System Based on Fingerprint Identification and Data Security Transmission.
J. Electr. Comput. Eng., 2017

2016
Byte-Based Partial-Match instruction and data compression for high-performance and low-power interconnects.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2014
Making games a "snap" with Stencyl: a summer computing workshop for K-12 teachers.
Proceedings of the 45th ACM Technical Symposium on Computer Science Education, 2014

2013
Going mobile with app inventor for android: a one-week computing workshop for K-12 teachers.
Proceedings of the 44th ACM Technical Symposium on Computer Science Education, 2013

Introducing programming concepts through video game creation.
Proceedings of the IEEE Frontiers in Education Conference, 2013

2012
Interconnect compression and its benefits for multi-core systems.
Proceedings of the IEEE 25th International SOC Conference, 2012

Computer science learning made interactive - A one-week alice summer computing workshop for K-12 teachers.
Proceedings of the IEEE Frontiers in Education Conference, 2012

An INSPIRED game programming academy for high school students.
Proceedings of the IEEE Frontiers in Education Conference, 2012

2011
INSPIRED High School Computing Academies.
ACM Trans. Comput. Educ., 2011

Introducing computer science to K-12 through a summer computing workshop for teachers.
Proceedings of the 42nd ACM technical symposium on Computer science education, 2011

A survey on computer science K-12 outreach: Teacher training programs.
Proceedings of the 2011 Frontiers in Education Conference, 2011

Work in progress - A survey of popular game creation platforms used for computing education.
Proceedings of the 2011 Frontiers in Education Conference, 2011

2010
Interconnect system compression analysis for multi-core architectures.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
Increasing Participation of Females and Underrepresented Minorities in Computing.
Computer, 2009

INSPIRED computing academies for middle school students: lessons learned.
Proceedings of the Richard Tapia Celebration of Diversity in Computing Conference 2009: Intellect, 2009

INSPIRED broadening participation: first year experience and lessons learned.
Proceedings of the 14th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2009

2008
The role of interconnects in the performance scalability of multicore architectures.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

2007
Pilot summer camps in computing for middle school girls: from organization through assessment.
Proceedings of the 12th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2007

2006
Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance.
Proceedings of the Interdisciplinary and Multidisciplinary Research in Computer Science, 2006

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost.
J. Instr. Level Parallelism, 2005

Energy-Efficient Compressed Address Transmission.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

The potential of compression to improve memory system performance, power consumption, and cost.
Proceedings of the 22nd IEEE International Performance Computing and Communications Conference, 2003

Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
The performance advantage of applying compression to the memory system.
Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002


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