Nihar R. Mahapatra

According to our database, Nihar R. Mahapatra authored at least 72 papers between 1993 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Hierarchical Deep Learning Models for Identification of Fish Species.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2022

A Study of Feature Importance in Fish Species Prediction Neural Networks.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2022

Deep Learning for Spatiotemporal Modeling of Illegal, Unreported, and Unregulated Fishing Events.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2022

2021

Multi-objective optimization of item selection in computerized adaptive testing.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the GECCO '21: Genetic and Evolutionary Computation Conference, 2021

Fish Species Classification with Data Augmentation.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2021

Convolutional Neural Networks for Morphologically Similar Fish Species Identification.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2021

Lateral Flow Test Interpretation with Residual Networks.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2021

Multi-Task Deep Neural Networks for Multimodal Personality Trait Prediction.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2021

2019

Ethical Considerations in AI-Based Recruitment.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the 2019 IEEE International Symposium on Technology and Society, 2019

Analysis of Affordance Detection Methods for Real-World Robotic Manipulation.

Xavier Williams, Nihar R. Mahapatra

Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

Modeling the Automation Level of Cyber-Physical Systems Designed for Food Preparation.

Dena F. Mujtaba, Nihar R. Mahapatra

Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

2018

Descriptor Data Bank (DDB): A Cloud Platform for Multiperspective Modeling of Protein-Ligand Interactions.

Hossam M. Ashtawy, Nihar R. Mahapatra

J. Chem. Inf. Model., 2018

Task-Specific Scoring Functions for Predicting Ligand Binding Poses and Affinity and for Screening Enrichment.

Hossam M. Ashtawy, Nihar R. Mahapatra

J. Chem. Inf. Model., 2018

Boosted neural networks scoring functions for accurate ligand docking and ranking.

Hossam M. Ashtawy, Nihar R. Mahapatra

J. Bioinform. Comput. Biol., 2018

2015

A Comparative Assessment of Predictive Accuracies of Conventional and Machine Learning Scoring Functions for Protein-Ligand Binding Affinity Prediction.

Hossam M. Ashtawy, Nihar R. Mahapatra

IEEE ACM Trans. Comput. Biol. Bioinform., 2015

Machine-learning scoring functions for identifying native poses of ligands docked to known and novel proteins.

Hossam M. Ashtawy, Nihar R. Mahapatra

BMC Bioinform., 2015

BgN-Score and BsN-Score: Bagging and boosting based ensemble neural networks scoring functions for accurate binding affinity prediction of protein-ligand complexes.

Hossam M. Ashtawy, Nihar R. Mahapatra

BMC Bioinform., 2015

2013

Does Accurate Scoring of Ligands against Protein Targets Mean Accurate Ranking?

Hossam M. Ashtawy, Nihar R. Mahapatra

Proceedings of the Bioinformatics Research and Applications, 9th International Symposium, 2013

Molecular Docking for Drug Discovery: Machine-Learning Approaches for Native Pose Prediction of Protein-Ligand Complexes.

Hossam M. Ashtawy, Nihar R. Mahapatra

Proceedings of the Computational Intelligence Methods for Bioinformatics and Biostatistics, 2013

2012

A Comparative Assessment of Ranking Accuracies of Conventional and Machine-Learning-Based Scoring Functions for Protein-Ligand Binding Affinity Prediction.

Hossam M. Ashtawy, Nihar R. Mahapatra

IEEE ACM Trans. Comput. Biol. Bioinform., 2012

2011

A Comparative Assessment of Conventional and Machine-Learning-Based Scoring Functions in Predicting Binding Affinities of Protein-Ligand Complexes.

Hossam M. Ashtawy, Nihar R. Mahapatra

Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2011

2010

Interconnect system compression analysis for multi-core architectures.

Jiangjiang Liu, Jianyong Zhang, Nihar R. Mahapatra

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009

Energy-Efficient Encoding for High-Performance Buses with Staggered Repeaters.

Sharath Jayaprakash, Nihar R. Mahapatra

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Dynamic User-Driven Available-Memory Non-Minimal Cost-Bounded Search.

Sandeep K. Namilikonda, Nihar R. Mahapatra

Proceedings of the 4th Indian International Conference on Artificial Intelligence, 2009

An Instance-Based Learning Approach for Available-Memory Non-minimal Cost-Bounded Search.

Sandeep K. Namilikonda, Nihar R. Mahapatra

Proceedings of the International Conference on Machine Learning and Applications, 2009

2008

Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass.

Kaushal R. Gandhi, Nihar R. Mahapatra

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

The role of interconnects in the performance scalability of multicore architectures.

Jiangjiang Liu, Nihar R. Mahapatra

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Slack redistribution in pipelined circuits for enhanced soft-error rate reduction.

Srivathsan Krishnamohan, Nihar R. Mahapatra

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Energy-optimal signaling and ordering of bits for area-constrained interconnects.

Sharath Jayaprakash, Nihar R. Mahapatra

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Partitioned reuse cache for energy-efficient soft-error protection of functional units.

Kaushal R. Gandhi, Nihar R. Mahapatra

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.

Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Enhancing Available-Memory Cost-Bounded Iterative-Deepening Search.

Sandeep K. Namilikonda, Nihar R. Mahapatra

Proceedings of the 2008 International Conference on Artificial Intelligence, 2008

2007

An efficient delay-optimal distributed termination detection algorithm.

Nihar R. Mahapatra, Shantanu Dutt

J. Parallel Distributed Comput., 2007

Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.

Sharath Jayaprakash, Nihar R. Mahapatra

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires.

Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 44th Design Automation Conference, 2007

2006

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses.

Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.

Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Value-based bit ordering for energy optimization of on-chip global signal buses.

Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits.

Kaushal R. Gandhi, Nihar R. Mahapatra

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost.

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, Srinivas Dangeti, Balakrishna V. Venkatrao

J. Instr. Level Parallelism, 2005

An Accurate Energy and Thermal Model for Global Signal Buses.

Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Energy-Efficient Compressed Address Transmission.

Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units.

Kaushal R. Gandhi, Nihar R. Mahapatra

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.

Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Increasing the energy efficiency of pipelined circuits via slack redistribution.

Srivathsan Krishnamohan, Nihar R. Mahapatra

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

An analysis of the robustness of CMOS delay elements.

Srivathsan Krishnamohan, Nihar R. Mahapatra

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Analysis and design of soft-error hardened latches.

Srivathsan Krishnamohan, Nihar R. Mahapatra

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Combining Error Masking and Error Detection Plus Recovery to Combat Soft Errors in Static CMOS Circuits.

Srivathsan Krishnamohan, Nihar R. Mahapatra

Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

2004

Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems.

Nihar R. Mahapatra, Shantanu Dutt

Parallel Comput., 2004

An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits.

Srivathsan Krishnamohan, Nihar R. Mahapatra

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.

Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits.

Srivathsan Krishnamohan, Nihar R. Mahapatra

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003

Code Compression Techniques for Embedded Systems and Their Effectiveness.

Krishnan Sundaresan, Nihar R. Mahapatra

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses.

Jiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

The potential of compression to improve memory system performance, power consumption, and cost.

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, Srinivas Dangeti, Balakrishna V. Venkatrao

Proceedings of the 22nd IEEE International Performance Computing and Communications Conference, 2003

Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis.

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units.

Kaushal R. Gandhi, Nihar R. Mahapatra

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002

The performance advantage of applying compression to the memory system.

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan

Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002

2001

Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays.

Nihar R. Mahapatra, Shantanu Dutt

J. Parallel Distributed Comput., 2001

2000

Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing.

Nihar R. Mahapatra, Shantanu Dutt

Int. J. Found. Comput. Sci., 2000

Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation.

Nihar R. Mahapatra, Sriram V. Garimella, Alwin Takeen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

The processor-memory bottleneck: problems and solutions.

Nihar R. Mahapatra, Balakrishna V. Venkatrao

XRDS, 1999

The role of computer technology trends in computer architecture education.

Nihar R. Mahapatra, Alwin Tareen

Proceedings of the 1999 workshop on Computer architecture education, 1999

A Quantitative Evaluation of Limited-Memory Branch-and-Bound Algorithms.

Nihar R. Mahapatra, Douglas E. Covelli, Yuval Beres

Proceedings of the International Conference on Artificial Intelligence, 1999

Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Digest of Papers: FTCS-29, 1999

1997

Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search.

Nihar R. Mahapatra, Shantanu Dutt

IEEE Trans. Parallel Distributed Syst., 1997

Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance.

Shantanu Dutt, Nihar R. Mahapatra

IEEE Trans. Computers, 1997

1996

Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Digest of Papers: FTCS-26, 1996

1994

Scalable Load Balancing Strategies for Parallel A* Algorithms.

Shantanu Dutt, Nihar R. Mahapatra

J. Parallel Distributed Comput., 1994

New Anticipatory Load Balancing Strategies for Parallel A* Algorithms.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Workshop on Parallel Processing of Discrete Optimization Problems, 1994

1993

Scalable Duplicate Pruning Strategies for Parallel A* Graph Search.

Nihar R. Mahapatra, Shantanu Dutt

Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Parallel A^* Algorithms and Their Performance on Hypercube Multiprocessors.

Shantanu Dutt, Nihar R. Mahapatra

Proceedings of the Seventh International Parallel Processing Symposium, 1993