Jieyu Jiang

Orcid: 0009-0001-6629-4967

According to our database1, Jieyu Jiang authored at least 6 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Tight Inter-Core Cache Contention Analysis for WCET Estimation on Multicore Systems.
CoRR, August, 2025

MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors.
CoRR, April, 2025

MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors.
ACM Trans. Embed. Comput. Syst., 2025

Tight Cache Contention Analysis for WCET Estimation on Multicore Systems.
Proceedings of the IEEE Real-Time Systems Symposium, 2025

2024
New Response Time Analysis for PWLP on Multiprocessor Mixed-Criticality Systems.
Proceedings of the 14th IEEE International Symposium on Industrial Embedded Systems, 2024

Resource-Aware Task Allocation on Mixed-Criticality Systems: a Task-Splitting Approach.
Proceedings of the 15th Asia-Pacific Symposium on Internetware, 2024


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