Jiliang Liu
Orcid: 0009-0006-6138-3879
According to our database1,
Jiliang Liu
authored at least 10 papers
between 2013 and 2025.
Collaborative distances:
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Bibliography
2025
ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2025
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025
Erratum: A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits [IEICE Electronics Express Vol. 20 (2023) No. 11 pp. 20230145].
IEICE Electron. Express, 2025
AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS.
IEEE Access, 2024
2023
A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits.
IEICE Electron. Express, 2023
Topology optimization base on stability of tainter gate arm considering multi-condition.
Proceedings of the International Conference on Mathematics and Machine Learning, 2023
2016
Compressed Sensing for Range-Resolved Signal of Ballistic Target with Low Computational Complexity.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
2015
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2013
Proceedings of the 2013 IEEE International Geoscience and Remote Sensing Symposium, 2013