A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation.

[BibT_eX]

[DOI]

Shukao Dou

Zupei Gu

IEEE Trans. Very Large Scale Integr. Syst., May, 2025

ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, May, 2025

A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

An ultra-low-power CMOS image sensor with a new pixel structure in PWM mode featuring a programmable ramp generator for calibration.

[BibT_eX]

[DOI]

Microelectron. J., 2025

A low-power and fast-response FSK transmitter.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

BitFleX: Exploiting extreme bit-level sparsity via BTD encoding and dynamic pruning.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

A 230 nW digital-based low noise bio-signal amplifier with symmetric differential-mode detection logic and cascaded Muller-C input stage.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

Erratum: A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits [IEICE Electronics Express Vol. 20 (2023) No. 11 pp. 20230145].

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

An SRAM-based chunked computing-in-memory macro with a multi-slope voltage-time-digital converting ADC for efficient MAC operations.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

An energy-efficient readout method based on weight-flip-store coding and quantization cycle skipping technology for computing in memory.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

Hardware Implementation of Block Floating-Point FFT Based on Approximate Computation and Conflict-Free Access.

[BibT_eX]

[DOI]

IEEE Access, 2025

Subset-Selection Weight Post-Training Quantization Method for Learned Image Compression Task.

[BibT_eX]

[DOI]

IEEE Access, 2025

An Area-Efficient Continuous-Time Ising Machine Featuring Dynamic Threshold Annealing.

[BibT_eX]

[DOI]

IEEE Access, 2025

An Ultra-Low-Power Fully-Static Contention-Free Single-Phase-Clock Flip-Flop With Low Area.

[BibT_eX]

[DOI]

IEEE Access, 2025

DIME-Net: A Dual-Illumination Adaptive Enhancement Network Based on Retinex and Mixture-of-Experts.

[BibT_eX]

[DOI]

Proceedings of the 33rd ACM International Conference on Multimedia, 2025

Hardware Friendly Transformer Optimization with Dynamic Attention Matrix Fusion.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A 230-nA Quiescent Current and Enhanced Transient Performance DC-DC Converter with Suppressed Under/Overshoot for IoT SoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

UPE: A Device-Edge DNN Inference Artificial Intelligence Processor with Supporting Reconfigurable Training.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

RSPE: A High Energy Efficient SNN Inference Processor with RISC-V based Dynamic Pruning Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

2024

A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A Low-Power and Low-Latency Speech Feature Extractor Based on Time-Domain Filter Bank.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Compressive Hyperspectral Target Detection With Restricted Distribution Property.

[BibT_eX]

[DOI]

IEEE Trans. Geosci. Remote. Sens., 2024

CS-TTD: Triplet Transformer for Compressive Hyperspectral Target Detection.

[BibT_eX]

[DOI]

IEEE Trans. Geosci. Remote. Sens., 2024

Differentiable architecture search with multi-dimensional attention for spiking neural networks.

[BibT_eX]

[DOI]

Neurocomputing, 2024

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

Energy-efficient approximate multiplier with incomplete-sorted 4-2 compressor for neural network applications.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS.

[BibT_eX]

[DOI]

IEEE Access, 2024

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks.

[BibT_eX]

[DOI]

IEEE Access, 2024

A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 0.5V 18.6nW Bandgap Voltage Reference with A Low-Leakage Sample / Hold Circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application.

[BibT_eX]

[DOI]

IEICE Electron. Express, December, 2023

A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

Blended Glial Cell's Spiking Neural Network.

[BibT_eX]

[DOI]

IEEE Access, 2023

AMA-Det: Enhancing Shared Head of One-Stage Object Detection With Adaptation, Merging, and Alignment.

[BibT_eX]

[DOI]

IEEE Access, 2023

An Ultra-Small Area and High-Sensitivity Wireless Receiver for ISM and MICS Band Application.

[BibT_eX]

[DOI]

Wenya Chen

Haohan Yang

Shushan Qiao

IEEE Access, 2023

A Binary Keyword Spotting System with Error-Diffusion Based Feature Binarization.

[BibT_eX]

[DOI]

Proceedings of the 24th Annual Conference of the International Speech Communication Association, 2023

Multi-grained Backend Fusion for Manipulation Region Location of Partially Fake Audio.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Deepfake Audio Detection and Analysis co-located with 32th International Joint Conference on Artificial Intelligence (IJCAI 2023), 2023

2022

A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM.

[BibT_eX]

[DOI]

IEICE Trans. Electron., November, 2022

An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Error-Diffusion Based Speech Feature Quantization for Small-Footprint Keyword Spotting.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2022

Correction: Zhang et al. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors 2022, 22, 5852.

[BibT_eX]

[DOI]

Sensors, 2022

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components.

[BibT_eX]

[DOI]

Sensors, 2022

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

A fully integrated GaAs HBT power amplifier with enhanced efficiency for 5-GHz WLAN applications.

[BibT_eX]

[DOI]

Haohan Yang

Heng You

Shushan Qiao

IEICE Electron. Express, 2022

A 0.6V 1.76nW power on reset circuit with high accuracy.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

A fully integrated RC oscillator with adaptive-body-biasing.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

Accurate spectral testing algorithm of ADC with amplitude drift.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

Low-complex and Highly-performed Binary Residual Neural Network for Small-footprint Keyword Spotting.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Conference of the International Speech Communication Association, 2022

Improving The ResNet-based Respiratory Sound Classification Systems With Focal Loss.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

Multi-type SRAM Test Structure with an Improved March LR Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Gradient Corrected Approximation for Binary Neural Networks.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2021

Area-energy efficient CORDICs using new elementary-angle-set and base-2 exponent expansions scheme.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2021

A 8.83nW, 0.14ppm/℃ crystal oscillator using duty-cycling automatic amplitude control.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2021

An Efficient im2row-Based Fast Convolution Algorithm for ARM Cortex-M MCUs.

[BibT_eX]

[DOI]

IEEE Access, 2021

A 0.5V 36nW 10-Transistor Power-on-Reset Circuit with High Accuracy.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital LSIs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Erratum: A low-overhead error detection and correction technique with a relaxed error timing constraint for variation-tolerance [IEICE Electronics Express Vol. 16 (2019) No. 14 pp. 20190342].

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

Erratum: Snake: An asynchronous pipeline for ultra-low-power applications [IEICE Electronics Express Vol. 16 (2019) No. 12 pp. 20190293].

[BibT_eX]

[DOI]

Zhi-jiu Zhu