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Jing Yu

Affiliations:
  • University of Manchester, UK
  • Royal Melbourne Institute of Technology (RMIT) University, School of Electrical & Computer Engineering, Melbourne, Australia (PhD 2019)


According to our database1, Jing Yu authored at least 4 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics.
[BibTeX]
[DOI]
King Lok Chung
,
Nguyen Dao
,
Jing Yu
,
Dirk Koch
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2021
The FABulous Open eFPGA Ecosystem in Action - From Specifications to Chips to Running Bitsteams.
[BibTeX]
[DOI]
Jing Yu
,
Andrew Attwood
,
Nguyen Dao
,
Dirk Koch
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

FABulous: An Embedded FPGA Framework.
[BibTeX]
[DOI]
Dirk Koch
,
Nguyen Dao
,
Bea Healy
,
Jing Yu
,
Andrew Attwood
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2014
A dual-rail LUT for reconfigurable logic using null convention logic.
[BibTeX]
[DOI]
Jing Yu
,
Paul Beckett
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014


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