Jinglong Xu
Orcid: 0000-0002-7677-6943
According to our database1,
Jinglong Xu
authored at least 4 papers
between 2019 and 2025.
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Bibliography
2025
2024
A 24% Efficient, 15.36 dBm Output Power, Multi-Standard Digital Polar Transmitter with 7-bit Phase Interpolator-based BFSK Modulator and 23 dB Sidelobe Suppressed PA for Low-Power Wide Area Networks.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency.
IEEE J. Solid State Circuits, 2023
2019
A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People.
IEEE Trans. Circuits Syst. Video Technol., 2019