Jinglong Xu

According to our database, Jinglong Xu authored at least 6 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A Multiband Ultralow-Power Transceiver With Two-Step Wake-Up Reception.

Thinh Tran-Dinh, Hafiz Usman Mahmood, Jinglong Xu, Keun-Mok Kim, Kyung-Sik Choi, Jaeheon Lee, Jinho Ko, Sang-Gug Lee, Jusung Kim

IEEE Solid State Circuits Lett., 2026

20.1 An Ultra-Compact Asymmetrically Load-Pulled Series Doherty Power Amplifier in 22Nm FDSOI CMOS with 25.3dBm Psat and 29.7% PAE6dB for Ku-Band 6G FR3.

Jinglong Xu, Tzu-Yuan Huang, Mohamed Eleraky, Islam Tolaib, Hua Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

Short-Term Power Load Forecasting Based on DPSO-LSSVM Model.

Shujun Ji, Linhao Zhang, Jinteng Wang, Tao Wei, Jiadong Li, Bu Ling, Jinglong Xu, Zuoping Wu

IEEE Access, 2025

2024

A 24% Efficient, 15.36 dBm Output Power, Multi-Standard Digital Polar Transmitter with 7-bit Phase Interpolator-based BFSK Modulator and 23 dB Sidelobe Suppressed PA for Low-Power Wide Area Networks.

Hafiz Usman Mahmood, Keun-Mok Kim, Thinh Tran-Dinh, Jinglong Xu, Abdul Qahir, Jinho Ko, Jusung Kim, Sang-Gug Lee, Kyung-Sik Choi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency.

Keun-Mok Kim, Kyung-Sik Choi, Hyunki Jung, Byeonghun Yun, Jinglong Xu, Jinho Ko, Sang-Gug Lee

IEEE J. Solid State Circuits, 2023

2019

A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People.

Xiaobai Chen, Jinglong Xu, Zhiyi Yu

IEEE Trans. Circuits Syst. Video Technol., 2019