Jinli Rao

According to our database, Jinli Rao authored at least 7 papers between 2010 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management.

Jinli Rao, Tianyong Ao, Kui Dai, Xuecheng Zou

IEEE Comput. Archit. Lett., 2019

2018

Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor.

Jinli Rao, Tianyong Ao, Shu Xu, Kui Dai, Xuecheng Zou

IEICE Trans. Inf. Syst., 2018

2016

BFWindow: Speculatively Checking Data Property Consistency against Buffer Overflow Attacks.

Jinli Rao, Zhangqing He, Shu Xu, Kui Dai, Xuecheng Zou

IEICE Trans. Inf. Syst., 2016

2014

A Compact Hardware Implementation of SM3 Hash Function.

Tianyong Ao, Zhangqing He, Jinli Rao, Kui Dai, Xuecheng Zou

Proceedings of the 13th IEEE International Conference on Trust, 2014

2011

Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture.

Dan Wu, Xuecheng Zou, Kui Dai, Jinli Rao, Pan Chen, Zhaoxia Zheng

J. Zhejiang Univ. Sci. C, 2011

2010

A High Efficient On-Chip Interconnection Network in SIMD CMPs.

Dan Wu, Kui Dai, Xuecheng Zou, Jinli Rao, Pan Chen

Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

The parallel algorithm implementation of matrix multiplication based on ESCA.

Pan Chen, Kui Dai, Dan Wu, Jinli Rao, Xuecheng Zou

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010