Joan Carletta

According to our database1, Joan Carletta authored at least 46 papers between 1994 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
An embeddable algorithm for gunshot detection.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A current and vibration based detection system for lightning strikes on transmission towers.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Energy consumption in long-range linear wireless sensor networks using LoRaWan and ZigBee.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
A study of hardware-friendly methods for gradient domain tone mapping of high dynamic range images.
J. Real Time Image Process., 2016

2015
A Booth-like modulo operator.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2013
A real-time implementation of gradient domain high dynamic range compression using a local Poisson solver.
J. Real Time Image Process., 2013

A Systematic Approach for Implementing Fractional-Order Operators and Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

A high-temperature comparator with rail-to-rail input voltage range.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A temperature and process insensitive CMOS reference current generator.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Embedding high dynamic range tone mapping in JPEG compression.
Proceedings of the Image Processing: Algorithms and Systems XI, 2013

2012
Instrumentation circuitry for an inductive wear debris sensor.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Teaching freshmen VHDL-based digital design.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
An analog logarithmic number system subtractor for edge detection in logarithmic CMOS image sensors.
Proceedings of the Sensors, 2011

2009
Exploiting redundancy to solve the Poisson equation using local information.
Proceedings of the International Conference on Image Processing, 2009

2008
A Fast JPEG2000 Encoder That Preserves Coding Efficiency: The Split Arithmetic Encoder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

High throughput JPEG2000 compatible encoder for high dynamic range images.
Proceedings of the International Conference on Image Processing, 2008

2007
An FPGA-based architecture for a local tone-mapping operator.
J. Real Time Image Process., 2007

A High Throughput Encoder for High Dynamic Range Images.
Proceedings of the International Conference on Image Processing, 2007

A PM Brushless DC Starter/Generator System for a Series-Parallel 2x2 Hybrid Electric Vehicle.
Proceedings of the Conference Record of the 2007 IEEE Industry Applications Conference Forty-Second IAS Annual Meeting, 2007

A real-time FPGA-based architecture for a Reinhard-like tone mapping operator.
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, 2007

2006
Multiplierless filter Bank design: structures that improve both hardware and image compression performance.
IEEE Trans. Circuits Syst. Video Technol., 2006

A Fast JPEG2000 EBCOT Tier-1 Architecture That Preserves Coding Efficiency.
Proceedings of the International Conference on Image Processing, 2006

FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
A methodology for FPGA-based control implementation.
IEEE Trans. Control. Syst. Technol., 2005

A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

An efficient architecture for lifting-based two-dimensional discrete wavelet transforms.
Integr., 2005

2004
Design of multiplierless, high-performance, wavelet filter banks with image compression applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Polyphase structures for multiplierless biorthogonal filter banks [image compression applications].
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Optimal quantized lifting coefficients for the 9/7 wavelet [image compression applications].
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Quantized FIR filter design using compensating zeros.
IEEE Signal Process. Mag., 2003

Implementation of digital fixed-point approximations to continuous-time IIR filters.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Determining appropriate precisions for signals in fixed-point IIR filters.
Proceedings of the 40th Design Automation Conference, 2003

FPGA-based implementation of digital control for a magnetic bearing.
Proceedings of the American Control Conference, 2003

2002
Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Integrated test of interacting controllers and datapaths.
ACM Trans. Design Autom. Electr. Syst., 2001

2000
An Evaluation of Move-Based Multi-Way Partitioning Algorithms.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A Direct Mapping FPGA Architecture for Industrial Process Control Applications.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Detecting Undetectable Controller Faults Using Power Analysis.
Proceedings of the 2000 Design, 2000

Synthesis-for-testability of controller-datapath pairs that use gated clocks.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs.
Proceedings of the 1999 Design, 1999

1997
Behavioral Testability Insertion for Datapath/Controller Circuits.
J. Electron. Test., 1997

A Scheme for Integrated Controller-Datapath Fault Testing.
Proceedings of the 34st Conference on Design Automation, 1997

1995
Test Synthesis in the Behavioral Domain.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Testability analysis and insertion for RTL circuits based on pseudorandom BIST.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A method for testability analysis and BIST insertion at the RTL.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Structural constraints for circular self-test paths.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994


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