Christos A. Papachristou

IEEE Access, 2023

Explainable Neural Network Recognition of Handwritten Characters.

[BibT_eX]

[DOI]

Paul Whitten

Proceedings of the 13th IEEE Annual Computing and Communication Workshop and Conference, 2023

2020

Design Space Exploration Driven by Lifetime Concerns due to Electromigration.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019

Methodology for Tradeoffs between Performance and Lifetimes of Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2015

Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication.

[BibT_eX]

[DOI]

Raed Bani-Hani

J. Circuits Syst. Comput., 2015

A robust authentication methodology using physically unclonable functions in DRAM arrays.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Knowledge-Guided Methodology for Third-Party Soft IP Analysis.

[BibT_eX]

[DOI]

Bhanu Negi

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Cross-correlation of specification and RTL for soft IP analysis.

[BibT_eX]

[DOI]

Arunprasath Shankar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Ontology-guided Conceptual Analysis of Design Specifications.

[BibT_eX]

[DOI]

Arunprasath Shankar

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis.

[BibT_eX]

[DOI]

Seetharam Narasimhan

Dongdong Du

Kaushik Roy

IEEE Trans. Computers, 2013

High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs.

[BibT_eX]

[DOI]

Cheng-Wen Wu

Proceedings of the International Symposium on Quality Electronic Design, 2013

Knowledge-Guided Methodology for Specification Analysis.

[BibT_eX]

[DOI]

Jim Morrison

Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

NEFCIS: Neuro-fuzzy Concept Based Inference System for Specification Mining.

[BibT_eX]

[DOI]

Arunprasath Shankar

Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

Expert System Simulation of Hardware.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Tools with Artificial Intelligence, 2013

2012

An efficient elliptic curve cryptography processor using addition chains with high information entropy.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

A low power memory cell design for SEU protection against radiation effects.

[BibT_eX]

[DOI]

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011

Smoothing delay jitter in networked control systems.

[BibT_eX]

[DOI]

Huthaifa Al-Omari

J. Embed. Comput., 2011

A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Noise margin, critical charge and power-delay tradeoffs for SRAM design.

[BibT_eX]

[DOI]

Frank Wolff

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Fast binary/decimal adder/subtractor with a novel correction-free BCD addition.

[BibT_eX]

[DOI]

Khaldoon Mhaidat

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Fast and compact binary-to-BCD conversion circuits for decimal multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

An analysis of efficient formulas for elliptic curve point addition over binary extension fields.

[BibT_eX]

[DOI]

Proceedings of the 45st Annual Conference on Information Sciences and Systems, 2011

2010

Trustworthy computing in a multi-core system using distributed scheduling.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.

[BibT_eX]

[DOI]

Seetharam Narasimhan

Dongdong Du

Kaushik Roy

Proceedings of the HOST 2010, 2010

Embedded system protection from software corruption.

[BibT_eX]

[DOI]

Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Process reliability based trojans through NBTI and HCI effects.

[BibT_eX]

[DOI]

Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

System level self-healing for parametric yield and reliability improvement under power bound.

[BibT_eX]

[DOI]

Seetharam Narasimhan

Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009

Exploiting Semiconductor Properties for Hardware Trojans

[BibT_eX]

[DOI]

CoRR, 2009

Hardware Trojan by Hot Carrier Injection

[BibT_eX]

[DOI]

CoRR, 2009

An Improved Algorithm to Smooth Delay Jitter in Cyber-Physical Systems.

[BibT_eX]

[DOI]

Huthaifa Al-Omari

Proceedings of the International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, 2009

SRAM cell design using tri-state devices for SEU protection.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Efficient architectures for elliptic curve cryptography processors for RFID.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Dynamic Evaluation of Hardware Trust.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Avoiding Delay Jitter in Cyber-Physical Systems Using One Way Delay Variations Model.

[BibT_eX]

[DOI]

Huthaifa Al-Omari

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

MERO: A Statistical Approach for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

An Adaptable Task Manager for Reconfigurable Architecture Kernels.

[BibT_eX]

[DOI]

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008

SRAM Cell Design Protected from SEU Upsets.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Multi-label imbalanced data enrichment process in neural net classifier training.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2008

An Embedded Flash Memory Vault for Software Trojan Protection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

A high-speed radix-4 multiplexer-based array multiplier.

[BibT_eX]

[DOI]

Dimitris Bekiaris

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Face Recognition using a Cognitive Processing Model.

[BibT_eX]

[DOI]

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007

An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Facial Image Associative Memory Model.

[BibT_eX]

[DOI]

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure.

[BibT_eX]

[DOI]

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006

A method for detecting interconnect DSM defects in systems on chip.

[BibT_eX]

[DOI]

Shih-Yu Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Self Test Program Design Technique for Embedded DSP Cores.

[BibT_eX]

[DOI]

Hani Rizk

J. Electron. Test., 2006

FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Dynamic Reconfigurable Fabric for Platform SoCs.

[BibT_eX]

[DOI]

J. Weaver

R. Vijayakumar

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Soft delay error analysis in logic circuits.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Self-Configurable Neural Network Processor for FIR Filter Applications.

[BibT_eX]

[DOI]

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

A Large Scale Adaptable Multiplier for Cryptographic Applications.

[BibT_eX]

[DOI]

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005

Node sensitivity analysis for soft errors in CMOS logic.

[BibT_eX]

[DOI]

Norbert Seifert

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM.

[BibT_eX]

[DOI]

Michael Nicolaidis

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only).

[BibT_eX]

[DOI]

Jianchun Li

Raj Shekhar

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories.

[BibT_eX]

[DOI]

Michael Nicolaidis

Steven L. Garverick

Proceedings of the 2005 Design, 2005

2004

Soft Delay Error Effects in CMOS Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A "Brick" Caching Scheme for 3D Medical Imaging.

[BibT_eX]

[DOI]

Jianchun Li

Raj Shekhar

Proceedings of the 2004 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2004

A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing.

[BibT_eX]

[DOI]

Jianchun Li

Raj Shekhar

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Test Compression and Hardware Decompression for Scan-Based SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Designing Self Test Programs for Embedded DSP Cores.

[BibT_eX]

[DOI]

Hani Rizk

Proceedings of the 2004 Design, 2004

2003

A Technique for High Ratio LZW Compression.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

False path exclusion in delay analysis of RTL structures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Multiscan-Based Test Compression and Hardware Decompression Using LZ77.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Integrated test of interacting controllers and datapaths.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

Breaking Correlation to Improve Testability.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Detection of text strings from mixed text/graphics images.

[BibT_eX]

[DOI]

Chien-Hua Tsai

Proceedings of the Document Recognition and Retrieval VIII, 2001

Improving Bus Test Via I<sub>DDT</sub> and Boundary Scan.

[BibT_eX]

[DOI]

Shih-Yu Yang

Massood Tabib-Azar

Proceedings of the 38th Design Automation Conference, 2001

Test Strategies for BIST at the Algorithmic and Register-Transfer Levels.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Stability-based algorithms for high-level synthesis of digital ASICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

An ILP formulation to optimize test access mechanism in system-on-chip testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Detecting Undetectable Controller Faults Using Power Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Synthesis-for-testability of controller-datapath pairs that use gated clocks.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

A multiple clocking scheme for low-power RTL design.

[BibT_eX]

[DOI]

Mark Spining

IEEE Trans. Very Large Scale Integr. Syst., 1999

Structural Fault Testing of Embedded Cores Using Pipelining.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Instruction Randomization Self Test For Processor Cores.

[BibT_eX]

[DOI]

Ken Batcher

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

High Time for Higher Level BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A Method of Distributed Controller Design for RTL Circuits.

[BibT_eX]

[DOI]

Yusuf Alzazeri

Proceedings of the 1999 Design, 1999

Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Microprocessor Based Testing for Core-Based System on Chip.

[BibT_eX]

[DOI]

F. Martin

Proceedings of the 36th Conference on Design Automation, 1999

Using codesign techniques to support analog functionality.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

High-Level Test Synthesis for Behavioral and Structural Designs.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Testability Enhancement for Control-Flow Intensive Behaviors.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Parallelism in Structural Fault Testing of Embedded Cores.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Testing DSP Cores Based on Self-Test Programs.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

A Bypass Scheme for Core-Based System Fault Testing.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Behavioral Testability Insertion for Datapath/Controller Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1997

Testability Enhancement for Behavioral Descriptions Containing Conditional Statements.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

A test synthesis technique using redundant register transfers.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Structural BIST insertion using behavioral test analysis.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

A Scheme for Integrated Controller-Datapath Fault Testing.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

BIST testability enhancement using high level test synthesis for behavioral and structural designs.

[BibT_eX]

[DOI]

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Hardware-Software Co-Design for Test: It's the Last Straw!

[BibT_eX]

[DOI]

Janusz Rajski

John W. Sheppard

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Synthesis of reusable DSP cores based on multiple behaviors.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

False path exclusion in delay analysis of RTL-based datapath-controller designs.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

COMET: a hardware-software codesign methodology.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

An evolution programming approach on multiple behaviors for the design of application specific programmable processors.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

An Effective Power Management Scheme for RTL Design Based on Multiple Clocks.

[BibT_eX]

[DOI]

Mark Spining

Proceedings of the 33st Conference on Design Automation, 1996

A Register File and Scheduling Model for Application Specific Processor Synthesis.

[BibT_eX]

[DOI]

Ehat Ercanli

Proceedings of the 33st Conference on Design Automation, 1996

BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design.

[BibT_eX]

[DOI]

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.

[BibT_eX]

[DOI]

Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Test Synthesis in the Behavioral Domain.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Testability analysis and insertion for RTL circuits based on pseudorandom BIST.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Architectural partitioning of control memory for application specific programmable processors.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A method for testability analysis and BIST insertion at the RTL.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Structural constraints for circular self-test paths.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

1993

Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing.

[BibT_eX]

[DOI]

Venkata R. Immaneni

IEEE Trans. Computers, 1993

A VLIW architecture based on shifting register files.

[BibT_eX]

[DOI]

H. Fatih Ugurdag

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A Partial Scan Cost Estimation Method at the System Level.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

An improved method for RTL synthesis with testability tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Approach for Redesigning in Data Path Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

A Layout Estimation Algorithm for RTL Datapaths.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

A Feedforward Neural Network Classifier Model: Multiple Classes, Confidence Output Values, and Implementation.

[BibT_eX]

[DOI]

George Georgiou

Int. J. Pattern Recognit. Artif. Intell., 1992

Y-Pipe: a conditional branching scheme without pipeline delays.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

ALMP: A Shifting Memory Architecture for Loop Pipelining.

[BibT_eX]

[DOI]

H. Fatih Ugurdag

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

A neural network based algorithm for the scheduling problem in high-level synthesis.

[BibT_eX]

[DOI]

Yoshiyasu Takefuji

Proceedings of the conference on European design automation, 1992

SYNTEST: an environment for system-level design for test.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Microcontrol architectures with sequencing firmware and modular microcode development tools.

[BibT_eX]

[DOI]

Satnamsingh B. Gambhir

Microprocessing and Microprogramming, 1991

SYNTEST: A Method for High-Level SYNthesis with Self-TESTability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Built-In Self-Testing Approach for Minimizing Hardware Overhead.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A Data Path Synthesis Method for Self-Testable Designs.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

A Design for Testability Scheme with Applications to Data Path Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

A design scheme for PLA-based control tables with reduced area and time-delay cost.

[BibT_eX]

[DOI]

Anil L. Pandya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

SMDSS - a structured microcode development and simulation system.

[BibT_eX]

[DOI]

Djahida Smati

Jerry P.-C. Hwang

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

An instruction reoderer for pipelined computers.

[BibT_eX]

[DOI]

Jong-Jiann Shieh

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

Extending Athena: multiple classes and confidence output values.

[BibT_eX]

[DOI]

George Georgiou

Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence, 1990

A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm.

[BibT_eX]

[DOI]

Haluk Konuk

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

On reordering instruction streams for pipelined computers.

[BibT_eX]

[DOI]

Jong-Jiann Shieh

Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

A Scheme for Overlaying Concurrent Testing of VLSI Circuits.

[BibT_eX]

[DOI]

Wen-Ben Jone

M. Pereira

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing.

[BibT_eX]

[DOI]

Wen-Ben Jone

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Mapping of micro data flow computations on parallel microarchitectures.

[BibT_eX]

[DOI]

L. Shih

Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

Training of a neural network for pattern classification based on an entropy measure.

[BibT_eX]

[DOI]

Proceedings of International Conference on Neural Networks (ICNN'88), 1988

1987

Associative table lookup processing for multioperand residue arithmetic.

[BibT_eX]

[DOI]

J. ACM, 1987

A Systolic Array Structure for Matrix Multiplication in the Residue Number System.

[BibT_eX]

[DOI]

Suntae Hwang

Proceedings of the Supercomputing, 1987

1986

Data flow graph partitioning to reduce communication cost.

[BibT_eX]

[DOI]

Ranga Vemuri

Proceedings of the 19th annual workshop on Microprogramming, 1986

Expert system approach to VLSI cell design (abstract).

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Annual Conference on Computer Science, 1986

1985

An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories.

[BibT_eX]

[DOI]

Narendar B. Sahgal

IEEE Trans. Computers, 1985

Microcode development for microprogrammed processors.

[BibT_eX]

[DOI]

Jerry P.-C. Hwang

Danny D. Cornett

Proceedings of the 18th annual workshop on Microprogramming, 1985

Multi - Input residue arithmetic utilizing read - Only associative memory.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1984

An automatic migration scheme based on modular microcode and structured firmware sequencing.

[BibT_eX]

[DOI]

Venkata R. Immaneni

D. B. Sarma

Proceedings of the 17th annual workshop on Microprogramming, 1984

1983

Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1983

1982

A microsequencer architecture with firmware support for modular microprogramming.

[BibT_eX]

[DOI]

Satnam Sing Gambhir

Proceedings of the 15th annual workshop on Microprogramming, 1982

1981

Hardware microcontrol schemes using PLAs.

[BibT_eX]

[DOI]

Proceedings of the 14th annual workshop on Microprogramming, 1981

Algorithms for parallel addition and parallel polynomial evaluation.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

1978

An Algorithm for Optimal NAND Cascade Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1978

1977

Characteristic measures of switching functions.

[BibT_eX]

[DOI]