João Navarro

According to our database, João Navarro authored at least 28 papers between 1995 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Low-Noise Amplifier in Submicron CMOS for Neural Recording on Optogenetics Applications.

Helder Eiki Oshiro, Rodrigo de A. P. Andrade, João Navarro Soares Junior, Maximiliam Luppe, Eduardo Colombari, M. Celeste Dias, João Paulo Carmo

Proceedings of the 18th International Joint Conference on Biomedical Engineering Systems and Technologies, 2025

Development of Optrodes and Instrumentation for Wireless Optogenetic Application.

Helder Eiki Oshiro, Rodrigo de A. P. Andrade, João Navarro Soares Junior, Maximiliam Luppe, Eduardo Colombari, M. Celeste Dias, João Paulo Carmo

Proceedings of the 18th International Joint Conference on Biomedical Engineering Systems and Technologies, 2025

2024

A Divide-by-1.5/2 Prescaler Utilizing Double Data Rate Technique.

Lucas Daudt Franck, João Navarro, João Paulo Carmo

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

2021

Charge-Pump Circuit in 65nm CMOS for Neural Stimulation on Deep-Brain Stimulation.

Tiago Mateus Nordi, V. M. Barbosa, R. H. Gounella, Godfred Asan, Maximiliam Luppe, João Navarro Soares Junior, João Paulo Carmo, Erich Talamoni Fonoff, Eduardo Colombari

Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020

Performance Comparison of High-Speed Dual Modulus Prescalers Using Metaheuristic Sizing/Optimization.

João Navarro, Maximiliam Luppe

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2019

Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS.

Arthur Lombardi Campos, João Navarro, Maximiliam Luppe

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

2014

Design for Stability of Active Inductor with Feedback Resistance.

Gabriel R. Guerreiro, João Navarro

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

2013

A CMOS bandgap reference circuit with a temperature coefficient adjustment block.

Eder Issao Ishibe, João Navarro Soares

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

A bandgap circuit with a temperature coefficient adjustment block.

Eder Issao Ishibe, João Navarro Soares Junior

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Design of an OTA-Miller for a 96dB SNR SC multi-bit Sigma-Delta modulator based on gm/ID methodology.

Heiner Alarcon Cubas, João Navarro Soares Jr.

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A power optimized decimator for sigma-delta data converters.

Dionisio de Carvalho, João Navarro

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012

Top-down design for Low power Multi-bit Sigma-Delta Modulator.

Heiner Alarcon Cubas, João Navarro Soares Jr.

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2011

Design of high speed digital circuits with E-TSPC cell library.

João Navarro Jr., Gustavo Campos Martins

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

A simple CMOS bandgap reference circuit with sub-1-V operation.

João Navarro Soares, Eder Ishibe

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2007

A 4.1 GHz prescaler using double data throughput E-TSPC structures.

Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter.

Hugo Daniel Hernández, Wilhelmus A. M. Van Noije, Elkim Roa, João Navarro Jr.

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures.

Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Mismatch effect analyses in CMOS tapered buffers.

Alexandre J. Aragão, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.

Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

2004

A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.

Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003

A Methodology for CMOS Low Noise Ampli.er Design.

Elkim Roa, João Navarro Soares, Wilhelmus A. M. Van Noije

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2002

Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design.

João Navarro Jr., Wilhelmus A. M. Van Noije

IEEE Trans. Very Large Scale Integr. Syst., 2002

2000

The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput.

João Navarro Soares, Wilhelmus A. M. Van Noije

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999

A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC).

João Navarro Soares, Wilhelmus A. M. Van Noije

IEEE J. Solid State Circuits, 1999

1998

Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology.

João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation.

João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems.

João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1995

Precise final state determination of mismatched CMOS latches.

Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr.

IEEE J. Solid State Circuits, May, 1995