João Navarro Jr.

According to our database, João Navarro Jr. authored at least 17 papers between 1995 and 2013.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2013

A CMOS bandgap reference circuit with a temperature coefficient adjustment block.

Eder Issao Ishibe, Joao Navarro Soares

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

2011

Design of high speed digital circuits with E-TSPC cell library.

João Navarro Jr., Gustavo Campos Martins

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

A simple CMOS bandgap reference circuit with sub-1-V operation.

Joao Navarro Soares, Eder Ishibe

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2007

A 4.1 GHz prescaler using double data throughput E-TSPC structures.

Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter.

Hugo Daniel Hernández, Wilhelmus A. M. Van Noije, Elkim Roa, João Navarro Jr.

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures.

Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Mismatch effect analyses in CMOS tapered buffers.

Alexandre J. Aragão, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.

Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

2004

A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.

Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

2003

A Methodology for CMOS Low Noise Ampli.er Design.

Elkim Roa, Joao Navarro Soares, Wilhelmus A. M. Van Noije

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2002

Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design.

João Navarro Jr., Wilhelmus A. M. Van Noije

IEEE Trans. Very Large Scale Integr. Syst., 2002

2000

The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput.

Joao Navarro Soares, Wilhelmus A. M. Van Noije

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999

A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC).

Joao Navarro Soares, Wilhelmus A. M. Van Noije

IEEE J. Solid State Circuits, 1999

1998

Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology.

João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation.

João Navarro Jr., Wilhelmus A. M. Van Noije

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems.

João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1995

Precise final state determination of mismatched CMOS latches.

Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr.

IEEE J. Solid State Circuits, May, 1995