Jofre Pallares

According to our database, Jofre Pallares authored at least 7 papers between 2003 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering.

Raul Quijada, Roger Dura, Jofre Pallares, Xavier Formatje, Salvador Hidalgo, Francisco Serra-Graells

J. Hardw. Syst. Secur., 2018

2017

Inkjet-Configurable Gate Arrays (IGA).

Jordi Carrabina, Mohammad Mashayekhi, Jofre Pallares Cuxart, Lluís Terés

IEEE Trans. Emerg. Top. Comput., 2017

An academic EDA suite for the full-custom design of mixed-mode integrated circuits.

Jofre Pallares, Keith Sabine, Lluís Terés, Francisco Serra-Graells

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2014

A 25-µW All-MOS Potentiostatic Delta-Sigma ADC for Smart Electrochemical Sensors.

Stepan Sutula, Jofre Pallares Cuxart, Javier Gonzalo-Ruiz, Francesc Xavier Munoz-Pascual, Lluís Terés, Francisco Serra-Graells

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Teaching mixed-mode full-custom VLSI design with gaf, SpiceOpus and Glade.

Stepan Sutula, Francesc Vila, Jofre Pallares, Keith Sabine, Lluís Terés, Francisco Serra-Graells

Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2007

A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator.

Xavier Redondo, Jofre Pallares, Francisco Serra-Graells

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2003

Modeling all-MOS log filters and its application to Sigma-Delta modulators.

Jofre Pallares, Justo Sabadell, Francisco Serra-Graells

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003