Johan Wernehag

According to our database1, Johan Wernehag authored at least 10 papers between 2008 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2017
Two Tunable Frequency Duplexer Architectures for Cellular Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
A 30dBm PA for MTC communication in 65nm CMOS technology.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Comparison of two SiGe 2-stage E-band power amplifier architectures.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Low power, highly stable and wideband LNA for GNSS applications in SiGe technology.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2014
A 28 GHz SiGe QVCO and divider for an 81-86 GHz E-band beam steering transmitter PLL.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2013
Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012
Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011
Highly linear direct conversion receiver using customized on-chip balun.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

2008
60 GHz 130-nm CMOS second harmonic power amplifiers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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