Jon G. Bredeson

According to our database, Jon G. Bredeson authored at least 16 papers between 1967 and 1994.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1994

Real-Time Study of a High Performance Protocol for Local/Metropolitan Ring Networks.

Hamid Barghi, William T. Cronenwett, Jon G. Bredeson

Proceedings of the Proceedings 19th Conference on Local Computer Networks, 1994

1980

Minimal Redundant Logic for High Reliability and Irredundant Testability.

John C. Sutton, Jon G. Bredeson

IEEE Trans. Computers, 1980

1978

A Method to Simplify a Boolean Function into a Near Minimal Sum-of-Products for Programmable Logic Arrays.

Zosimo Arevalo, Jon G. Bredeson

IEEE Trans. Computers, 1978

Computer-assisted data communications engineering instruction.

N. W. Styer, Jon G. Bredeson

Proceedings of the IEEE Computer Society's Second International Computer Software and Applications Conference, 1978

1975

Comments on "Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops".

Jon G. Bredeson

IEEE Trans. Computers, 1975

1974

Comments on "Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks".

C. D. Latino, Jon G. Bredeson

IEEE Trans. Computers, 1974

1973

Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops.

Jon G. Bredeson, Paul T. Hulina

IEEE Trans. Computers, 1973

On Multiple Input Change Hazard-Free Combinatorial Switching Circuits without Feedback

Jon G. Bredeson

Proceedings of the 14th Annual Symposium on Switching and Automata Theory, 1973

1972

Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits

Jon G. Bredeson, Paul T. Hulina

Inf. Control., March, 1972

1971

Generation of Prime Implicants by Direct Multiplication.

Jon G. Bredeson, Paul T. Hulina

IEEE Trans. Computers, 1971

Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races.

Jon G. Bredeson, Paul T. Hulina

IEEE Trans. Computers, 1971

1970

On Tracey's Internal State Assignment Method.

Paul T. Hulina, Jon G. Bredeson

IEEE Trans. Computers, 1970

Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits

Jon G. Bredeson, Paul T. Hulina

Proceedings of the 11th Annual Symposium on Switching and Automata Theory, 1970

1969

Ternary graph theoretic error-correcting codes (Corresp.).

S. Louis Hakimi, Jon G. Bredeson

IEEE Trans. Inf. Theory, 1969

1968

Graph theoretic error-correcting codes.

Seifollah Louis Hakimi, Jon G. Bredeson

IEEE Trans. Inf. Theory, 1968

1967

Decoding of graph theoretic codes (Corresp.).

Jon G. Bredeson, Seifollah Louis Hakimi

IEEE Trans. Inf. Theory, 1967