Paul T. Hulina

Sanjay Balasubramanian

Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Computing in Memory Architectures for Digital Image Processing.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Evaluation of Computing in Memory Architectures for Digital Image Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

1997

A WWW facilitated rapid system prototyping class.

[BibT_eX]

[DOI]

David L. Landis

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

An electronics manufacturing minor in engineering with emphasis on rapid prototyping.

[BibT_eX]

[DOI]

David L. Landis

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

1995

Program Balance and Its Impact on High Performance RISC Architectures.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

A comparative evaluation of software techniques to hide memory latency.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994

Memory Latency Effects in Decoupled Architectures.

[BibT_eX]

[DOI]

Lizyamma Kurian

IEEE Trans. Computers, 1994

Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories.

[BibT_eX]

[DOI]

Proceedings of the 1994 International Conference on Parallel Processing, 1994

Structured Data Access Mechanisms for a Decoupled Computer Architecture.

[BibT_eX]

[DOI]

Ali Berrached

Proceedings of the 1994 International Conference on Parallel Processing, 1994

1992

Design and VLSI implementation of an access processor for a decoupled architecture.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1992

Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module.

[BibT_eX]

[DOI]

Lizyamma Kurian

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991

Classification and Performance Evaluation of Instruction Buffering Techniques.

[BibT_eX]

[DOI]

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

Performance Analysis of an Address Generation Coprocessor.

[BibT_eX]

Shih-Wei Sun

Proceedings of the International Conference on Parallel Processing, 1991

1990

Coprocessor architectures for efficient address computation and memory accessing.

[BibT_eX]

Comput. Syst. Sci. Eng., 1990

1987

A General Model for Memory-Based Finite-State Machines.

[BibT_eX]

[DOI]

Orlando A. Morean

IEEE Trans. Computers, 1987

A Hardware Memory Mapping Unit for Efficient Address Computation.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1987

1985

A Reconfigurable Multiprocessor.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1985

1973

Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1973

1972

Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits

[BibT_eX]

[DOI]

Inf. Control., March, 1972

1971

Generation of Prime Implicants by Direct Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1971

Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1971

1970

On Tracey's Internal State Assignment Method.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1970

Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits

[BibT_eX]

[DOI]

Proceedings of the 11th Annual Symposium on Switching and Automata Theory, 1970

The binary floating point digital differential analyzer.

[BibT_eX]

[DOI]

James L. Elshoff