Jongeun Koo

According to our database1, Jongeun Koo authored at least 9 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2021
Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations.
IEEE J. Solid State Circuits, 2021

2020
A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines.
IEICE Electron. Express, 2019

Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2017
Low design overhead timing error correction scheme for elastic clock methodology.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2011
Fast power delivery network analyzer.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011


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