Jorge Surís

According to our database, Jorge Surís authored at least 9 papers between 2006 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

RapidRadio: Signal Classification and Radio Deployment Framework.

Jorge Alberto Surís, Adolfo Recio, Peter Athanas

ACM Trans. Embed. Comput. Syst., 2012

2011

On the Implementation of a Quasi-Generic Synchronization Architecture for Linear Digital Modulations.

Jorge Alberto Surís, Adolfo Recio, Peter M. Athanas

J. Signal Process. Syst., 2011

2010

RapidRadio: A Domain-Specific Productivity Enhancing Framework.

Jorge Alberto Surís, Adolfo Recio, Peter M. Athanas

Int. J. Reconfigurable Comput., 2010

Automatic modulation classification for rapid radio deployment.

Adolfo Recio, Jorge Alberto Surís, Peter Athanas

Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

2009

Slotless module-based reconfiguration of embedded FPGAs.

Cameron D. Patterson, Peter Athanas, Matthew Shelburne, John W. Bowen, Jorge Surís, T. Dunham, J. Rice

ACM Trans. Embed. Comput. Syst., 2009

Enhancing the Productivity of Radio Designers with RapidRadio.

Jorge Surís, Adolfo Recio, Peter Athanas

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008

An efficient run-time router for connecting modules in FPGAS.

Jorge Surís, Cameron D. Patterson, Peter Athanas

Proceedings of the FPL 2008, 2008

2007

Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing.

Peter M. Athanas, John W. Bowen, T. Dunham, Cameron D. Patterson, J. Rice, Matthew Shelburne, Jorge Surís, Mark B. Bucciero, Jonathan Graf

Proceedings of the FPL 2007, 2007

2006

Exploring Non-Traditional Hardware-Software Interaction.

Jorge Alberto Surís, Peter M. Athanas

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006