Jose Carlos Garcia-Montesdeoca

Orcid: 0000-0003-3907-5141

Affiliations:
  • University of Las Palmas de Gran Canaria, Institute for Applied Microelectronics, Information and Communication Systems, Spain


According to our database1, Jose Carlos Garcia-Montesdeoca authored at least 31 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Online presence:

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Bibliography

2022
High Gain, Low Noise and Power Transimpedance Amplifier Based on Second Generation Voltage Conveyor in 65 nm CMOS Technology.
Sensors, 2022

2019
Versatile CMOS Current Conveyor for Digital VLSI Systems with Low-Voltage Power Supply.
J. Low Power Electron., 2019

Current Mirror Based Low Voltage Single Supply CMOS Level up-Shifter.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

High Performance CMOS Level up Conversion for Systems with Low-Voltage Power Supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
High performance CMOS level up shifter with full-scale 1.2 V output voltage.
Microelectron. J., 2018

Low Swing Charge Recycling Driver for On-Chip Interconnect.
J. Low Power Electron., 2018

2017
High performance single supply CMOS 0.45-1 V input to 1.1 V output level up shifter.
Microelectron. J., 2017

1.2 V Single Supply CMOS Level-Up Shifter for Low Energy Systems.
J. Low Power Electron., 2017

Single supply CMOS Up level shifter for dual voltage system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
Design and Optimization of a Low Power Pressure Sensor for Wireless Biomedical Applications.
J. Sensors, 2015

High performance single supply CMOS level up/down shifter for multiple voltages.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

High performance single supply CMOS inverter level up shifter for multi: supply voltages domains.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2010
Application of Mixed Integer Linear Programming in the Generation of Vectors with Maximum Datapath Coverage for Combinational Logic Circuits.
J. Circuits Syst. Comput., 2010

Low-energy multi-path adiabatic CMOS driver for low-energy system applications with large capacitive load.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2009

CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects.
Microelectron. J., 2009

A geometric approach to register transfer level satisfiability.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Analysis and Comparison of High Performance CMOS Adiabatic Drivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Low energy CMOS true single phase power supply clocking adiabatic differential cascode voltage switch logic circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High performance bootstrapped CMOS low to high-swing level-converter for on-chip interconnects.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Efficient CMOS driver-receiver pair with low-swing signaling for on-chip interconnects.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
A Single-Capacitor Bootstrapped Power-Efficient CMOS Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Bootstrapped full-swing CMOS driver for low supply voltage operation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low Power Bootstrapped CMOS Differential Cross Coupled Driver.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004
Functional Vector Generation for Combinational Circuits Based on Data Path Coverage Metric and Mixed Integer Linear Programming.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit.
Proceedings of the 2004 Design, 2004


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