José Claudio Vieira S. Junior

Orcid: 0000-0003-3601-989X

According to our database1, José Claudio Vieira S. Junior authored at least 5 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
FPGA Applied to Latency Reduction for the Tactile Internet.
Sensors, 2022

2020
Reconfigurable Computing Applied to Latency Reduction for the Tactile Internet.
CoRR, 2020

2019
Proposal of the Tactile Glove Device.
Sensors, 2019

2016
Testing real-time embedded systems using high level architecture.
Des. Autom. Embed. Syst., 2016

2015
Testing Real-Time Embedded Systems with Hardware-in-the-Loop Simulation Using High Level Architecture.
Proceedings of the 2015 Brazilian Symposium on Computing Systems Engineering, 2015


  Loading...