Joseph A. Fisher

Affiliations:
  • University of Toronto, Canada


According to our database1, Joseph A. Fisher authored at least 37 papers between 1980 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2022
Quantifying cerebral blood arrival times using hypoxia-mediated arterial BOLD contrast.
NeuroImage, 2022

2018
The aging brain and cerebrovascular reactivity.
NeuroImage, 2018

2015
The dynamics of cerebrovascular reactivity shown with transfer function analysis.
NeuroImage, 2015

Examining the regional and cerebral depth-dependent BOLD cerebrovascular reactivity response at 7 T.
NeuroImage, 2015

2014
A conceptual model for CO<sub>2</sub>-induced redistribution of cerebral blood flow with experimental confirmation using BOLD MRI.
NeuroImage, 2014

Investigating the non-linearity of the BOLD cerebrovascular reactivity response to targeted hypo/hypercapnia at 7 T.
NeuroImage, 2014

2012
Measuring venous blood volume changes during activation using hyperoxia.
NeuroImage, 2012

2011
VLIW Processors.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Improved fMRI calibration: Precisely controlled hyperoxic versus hypercapnic stimuli.
NeuroImage, 2011

2010
The change in cerebrovascular reactivity between 3 T and 7 T measured using graded hypercapnia.
NeuroImage, 2010

BOLD signal responses to controlled hypercapnia in human spinal cord.
NeuroImage, 2010

2005
Embedded computing - a VLIW approach to architecture, compilers, and tools.
Morgan Kaufmann, ISBN: 978-1-55860-766-8, 2005

2003
Moving from embedded systems to embedded computing.
Proceedings of the International Conference on Compilers, 2003

2002
DELI: a new run-time control point.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

2001
Instruction scheduling for instruction level parallel processors.
Proc. IEEE, 2001

2000
Lx: a technology platform for customizable VLIW embedded processing.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1999
Customized Instruction-Sets for Embedded Processors.
Proceedings of the 36th Conference on Design Automation, 1999

1998
The latest word in digital and media processing.
IEEE Signal Process. Mag., 1998

Retrospective: Very Long Instruction Word Architectures and the ELI-512.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1997
Walk-Time Techniques: Catalyst for Architectural Change.
Computer, 1997

1996
Custom-fit Processors: Letting Applications Define Architectures.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1993
Instruction-level parallel processing: History, overview, and perspective.
J. Supercomput., 1993

Guest editors' introduction.
J. Supercomput., 1993

1992
Predicting Conditional Branch Directions From Previous Runs of a Program.
Proceedings of the ASPLOS-V Proceedings, 1992

1988
Microprogramming, microprocessing and supercomputing.
Microprocess. Microprogramming, 1988

1987
A New Architecture for Supercomputing.
Proceedings of the COMPCON'87, 1987

1984
Measuring the Parallelism Available for Very Long Instruction Word Architectures.
IEEE Trans. Computers, 1984

Microcode compaction: Extending the boundaries.
Int. J. Parallel Program., 1984

The VLIW Machine: A Multiprocessor for Compiling Scientific Code.
Computer, 1984

Parallel processing: a smart compiler and a dumb machine.
Proceedings of the 1984 SIGPLAN Symposium on Compiler Construction, 1984

Parallel processing: a smart compiler and a dumb machine (with retrospective)
Proceedings of the 20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation 1979-1999, 1984

VLIW Machines: Multiprocessors We Can Acutally Program.
Proceedings of the COMPCON'84, Digest of Papers, Twenty-Eighth IEEE Computer Society International Conference, San Francisco, California, USA, February 27, 1984

1983
Very Long Instruction Word Architectures and the ELI-512
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

1981
Trace Scheduling: A Technique for Global Microcode Compaction.
IEEE Trans. Computers, 1981

Using an oracle to measure potential parallelism in single instruction stream programs.
Proceedings of the 14th annual workshop on Microprogramming, 1981

Microcode compaction: looking backward and looking forward.
Proceedings of the American Federation of Information Processing Societies: 1981 National Computer Conference, 1981

1980
2n-way jump microinstruction hardware and an effective instruction binding method.
Proceedings of the 13th annual workshop on Microprogramming, 1980


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