Paolo Faraboschi

Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Computing In-Memory, Revisited.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018

2017

Separating Translation from Protection in Address Spaces with Dynamic Remapping.

[BibT_eX]

[DOI]

Proceedings of the 16th Workshop on Hot Topics in Operating Systems, 2017

2016

Evaluating and Improving the Performance and Scheduling of HPC Applications in Cloud.

[BibT_eX]

[DOI]

IEEE Trans. Cloud Comput., 2016

Parallel Graph Processing: Prejudice and State of the Art.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM/SPEC International Conference on Performance Engineering, 2016

A unified memory network architecture for in-memory computing in commodity servers.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Enabling technologies for memory compression: Metadata, mapping, and prediction.

[BibT_eX]

[DOI]

Rajeev Balasubramonian

Robert Schreiber

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

SpaceJMP: Programming with Multiple Virtual Address Spaces.

[BibT_eX]

[DOI]

Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.

[BibT_eX]

[DOI]

J. Supercomput., 2015

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2015

What Will 2022 Look Like? The IEEE CS 2022 Report.

[BibT_eX]

[DOI]

Computer, 2015

Evaluating the Combined Impact of Node Architecture and Cloud Workload Characteristics on Network Traffic and Performance/Cost.

[BibT_eX]

[DOI]

Mahmut Taylan Kandemir

Anand Sivasubramaniam

Chita R. Das

Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

Beyond Processor-centric Operating Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th Workshop on Hot Topics in Operating Systems, 2015

2014

TERAFLUX: Harnessing dataflow in next generation teradevices.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

An Introduction to DF-Threads and their Execution Model.

[BibT_eX]

[DOI]

Roberto Giorgi

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

2013

HPC-Aware VM Placement in Infrastructure Clouds.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Conference on Cloud Engineering, 2013

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

The Who, What, Why, and How of High Performance Computing in the Cloud.

[BibT_eX]

[DOI]

Proceedings of the IEEE 5th International Conference on Cloud Computing Technology and Science, 2013

2012

Top Picks from the 2011 Computer Architecture Conferences.

[BibT_eX]

[DOI]

T. N. Vijaykumar

IEEE Micro, 2012

Simulating the future kilo-x86-64 core processors and their infrastructure.

[BibT_eX]

[DOI]

Proceedings of the 2012 Spring Simulation Multiconference, 2012

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Exploring the performance and mapping of HPC applications to platforms in the cloud.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on High-Performance Parallel and Distributed Computing, 2012

2011

VLIW Processors.

[BibT_eX]

[DOI]

Parthasarathy Ranganathan

Cliff Young

Proceedings of the Encyclopedia of Parallel Computing, 2011

System-level integrated server architectures for scale-out datacenters.

[BibT_eX]

[DOI]

Norman P. Jouppi

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2009

COTSon: infrastructure for full system simulation.

[BibT_eX]

[DOI]

ACM SIGOPS Oper. Syst. Rev., 2009

How to simulate 1000 cores.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2009

High-speed network modeling for full system simulation.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

Operating System Support for NVM+DRAM Hybrid Main Memory.

[BibT_eX]

[DOI]

Proceedings of HotOS'09: 12th Workshop on Hot Topics in Operating Systems, 2009

2008

An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters.

[BibT_eX]

[DOI]

Ayose Falcón

Daniel Ortega

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

2007

Combining Simulation and Virtualization through Dynamic Sampling.

[BibT_eX]

[DOI]

Ayose Falcón

Daniel Ortega

Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

2005

Document digitization lifecycle for complex magazine collection.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM Symposium on Document Engineering, 2005

Embedded computing - a VLIW approach to architecture, compilers, and tools.

[BibT_eX]

Cliff Young

Morgan Kaufmann, ISBN: 978-1-55860-766-8, 2005

2002

DELI: a new run-time control point.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

A New Facility for Dynamic Control of Program Execution: DELI.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software, Second International Conference, 2002

2001

Instruction scheduling for instruction level parallel processors.

[BibT_eX]

[DOI]

Cliff Young

Proc. IEEE, 2001

2000

Lx: a technology platform for customizable VLIW embedded processing.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1998

The latest word in digital and media processing.

[BibT_eX]

[DOI]

Giuseppe Desoli

IEEE Signal Process. Mag., 1998

1996

Custom-fit Processors: Letting Applications Define Architectures.

[BibT_eX]

[DOI]

Giuseppe Desoli

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995

Hardware solutions for fuzzy control.

[BibT_eX]

[DOI]

Proc. IEEE, 1995

1994

Block placement with a Boltzmann Machine.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An evaluation system for distributed-time VHDL simulation.

[BibT_eX]

[DOI]

Proceedings of the Eighth Workshop on Parallel and Distributed Simulation, 1994

1993

Efficient implementation of the Boltzmann machine algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1993

Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems.

[BibT_eX]

[DOI]

Parallel Comput., 1993

Delay insensitive micro-pipelined combinational logic.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

Design of a massively parallel SIMD architecture for the Boltzmann machine.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

A delay insensitive approach to the VLSI design of a DRAM controller.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

A parallel architecture for the Color Doppler flow technique in ultrasound imaging.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

An asynchronous approach to the RISC design of a micro-controller.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

An analysis of dynamic scheduling techniques for symbolic applications.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992

A dedicated massively parallel architecture for the Boltzmann machine.

[BibT_eX]

[DOI]

Sandro Ridella

Parallel Comput., 1992

Massive parallelism in multi-level simulation of VLSI circuits.

[BibT_eX]

[DOI]

Integr., 1992

A non-deterministic scheduler for a software pipelining compiler.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Instruction-level Parallelism in Prolog: Analysis and Architectural Support.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991

A Boltzmann Machine approach to code optimization.

[BibT_eX]

[DOI]

Parallel Comput., 1991

1990

An evaluation system for application specific architectures.

[BibT_eX]

[DOI]