Paolo Faraboschi

According to our database1, Paolo Faraboschi authored at least 50 papers between 1990 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to embedded processor architecture and system-on-chip technology".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2018
Computing In-Memory, Revisited.
Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018

2017
Separating Translation from Protection in Address Spaces with Dynamic Remapping.
Proceedings of the 16th Workshop on Hot Topics in Operating Systems, 2017

2016
Evaluating and Improving the Performance and Scheduling of HPC Applications in Cloud.
IEEE Trans. Cloud Computing, 2016

Parallel Graph Processing: Prejudice and State of the Art.
Proceedings of the 7th ACM/SPEC International Conference on Performance Engineering, 2016

A unified memory network architecture for in-memory computing in commodity servers.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Enabling technologies for memory compression: Metadata, mapping, and prediction.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

SpaceJMP: Programming with Multiple Virtual Address Spaces.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015
Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.
The Journal of Supercomputing, 2015

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion.
TACO, 2015

What Will 2022 Look Like? The IEEE CS 2022 Report.
IEEE Computer, 2015

Evaluating the Combined Impact of Node Architecture and Cloud Workload Characteristics on Network Traffic and Performance/Cost.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

Beyond Processor-centric Operating Systems.
Proceedings of the 15th Workshop on Hot Topics in Operating Systems, 2015

2014
TERAFLUX: Harnessing dataflow in next generation teradevices.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

An Introduction to DF-Threads and their Execution Model.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

2013
HPC-Aware VM Placement in Infrastructure Clouds.
Proceedings of the 2013 IEEE International Conference on Cloud Engineering, 2013


The Who, What, Why, and How of High Performance Computing in the Cloud.
Proceedings of the IEEE 5th International Conference on Cloud Computing Technology and Science, 2013

2012
Top Picks from the 2011 Computer Architecture Conferences.
IEEE Micro, 2012

Simulating the future kilo-x86-64 core processors and their infrastructure.
Proceedings of the 2012 Spring Simulation Multiconference, 2012

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Exploring the performance and mapping of HPC applications to platforms in the cloud.
Proceedings of the 21st International Symposium on High-Performance Parallel and Distributed Computing, 2012

2011
VLIW Processors.
Proceedings of the Encyclopedia of Parallel Computing, 2011

System-level integrated server architectures for scale-out datacenters.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2009
COTSon: infrastructure for full system simulation.
Operating Systems Review, 2009

How to simulate 1000 cores.
SIGARCH Computer Architecture News, 2009

High-speed network modeling for full system simulation.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

Operating System Support for NVM+DRAM Hybrid Main Memory.
Proceedings of HotOS'09: 12th Workshop on Hot Topics in Operating Systems, 2009

2008
An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

2007
Combining Simulation and Virtualization through Dynamic Sampling.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

2005
Document digitization lifecycle for complex magazine collection.
Proceedings of the 2005 ACM Symposium on Document Engineering, 2005

Embedded computing - a VLIW approach to architecture, compilers, and tools.
Morgan Kaufmann, ISBN: 978-1-55860-766-8, 2005

2002
DELI: a new run-time control point.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

A New Facility for Dynamic Control of Program Execution: DELI.
Proceedings of the Embedded Software, Second International Conference, 2002

2000
Lx: a technology platform for customizable VLIW embedded processing.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1996
Custom-fit Processors: Letting Applications Define Architectures.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1994
Block placement with a Boltzmann Machine.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

1993
Efficient implementation of the Boltzmann machine algorithm.
IEEE Trans. Neural Networks, 1993

Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems.
Parallel Computing, 1993

Delay insensitive micro-pipelined combinational logic.
Microprocessing and Microprogramming, 1993

Design of a massively parallel SIMD architecture for the Boltzmann machine.
Microprocessing and Microprogramming, 1993

A delay insensitive approach to the VLSI design of a DRAM controller.
Microprocessing and Microprogramming, 1993

A parallel architecture for the Color Doppler flow technique in ultrasound imaging.
Microprocessing and Microprogramming, 1993

An asynchronous approach to the RISC design of a micro-controller.
Microprocessing and Microprogramming, 1993

An analysis of dynamic scheduling techniques for symbolic applications.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992
A dedicated massively parallel architecture for the Boltzmann machine.
Parallel Computing, 1992

Massive parallelism in multi-level simulation of VLSI circuits.
Integration, 1992

A non-deterministic scheduler for a software pipelining compiler.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Instruction-level Parallelism in Prolog: Analysis and Architectural Support.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991
A Boltzmann Machine approach to code optimization.
Parallel Computing, 1991

1990
An evaluation system for application specific architectures.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990


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