Paolo Faraboschi

Orcid: 0000-0003-4778-5696

  • Hewlett Packard Enterprise Labs, Palo Alto, CA, USA

According to our database1, Paolo Faraboschi authored at least 78 papers between 1990 and 2024.

Collaborative distances:


IEEE Fellow

IEEE Fellow 2014, "For contributions to embedded processor architecture and system-on-chip technology".



In proceedings 
PhD thesis 


Online presence:



Ethics in Sustainability.
IEEE Des. Test, February, 2024

What Gets You Hired Now Will Not Get You Hired Then.
IT Prof., 2024

Reducing the Barriers to Entry for Foundation Model Training.
CoRR, 2024

Artificial General Intelligence: Humanity's Downturn or Unlimited Prosperity.
Computer, October, 2023

Digital Transformation: Lights and Shadows.
Computer, April, 2023

X-TIME: An in-memory engine for accelerating machine learning on tabular data with CAMs.
CoRR, 2023

Computer, 2023

Future of the Workforce.
Computer, 2023

Towards Rapid Autonomous Electron Microscopy with Active Meta-Learning.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Virtual Worlds (Metaverse): From Skepticism, to Fear, to Immersive Opportunities.
Computer, 2022

Self-learning Data Foundation for Scientific AI.
Proceedings of the Accelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation, 2022

Multi-Agent Reinforcement Learning Controller to Maximize Energy Efficiency for Multi-Generator Industrial Wave Energy Converter.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

Future of HPC: The Internet of Workflows.
IEEE Internet Comput., 2021

A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper).
Proceedings of the IEEE/ACM Programming Environments for Heterogeneous Computing, 2021

Data-Aware Storage Tiering for Deep Learning.
Proceedings of the 6th IEEE/ACM International Parallel Data Systems Workshop, 2021

Future of HPC: Diversifying Heterogeneity.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Memory-Side Protection With a Capability Enforcement Co-Processor.
ACM Trans. Archit. Code Optim., 2019

Technology Predictions: Art, Science, and Fashion.
Computer, 2019

Rack-Scale Capabilities: Fine-Grained Protection for Large-Scale Memories.
Computer, 2019

Gen-Z Chipsetfor Exascale Fabrics.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Computing in the Cambrian Era Plenary Talk.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Computing In-Memory, Revisited.
Proceedings of the 38th IEEE International Conference on Distributed Computing Systems, 2018

Separating Translation from Protection in Address Spaces with Dynamic Remapping.
Proceedings of the 16th Workshop on Hot Topics in Operating Systems, 2017

Evaluating and Improving the Performance and Scheduling of HPC Applications in Cloud.
IEEE Trans. Cloud Comput., 2016

Parallel Graph Processing: Prejudice and State of the Art.
Proceedings of the 7th ACM/SPEC International Conference on Performance Engineering, 2016

A unified memory network architecture for in-memory computing in commodity servers.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Enabling technologies for memory compression: Metadata, mapping, and prediction.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

SpaceJMP: Programming with Multiple Virtual Address Spaces.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.
J. Supercomput., 2015

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion.
ACM Trans. Archit. Code Optim., 2015

What Will 2022 Look Like? The IEEE CS 2022 Report.
Computer, 2015

Evaluating the Combined Impact of Node Architecture and Cloud Workload Characteristics on Network Traffic and Performance/Cost.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

Beyond Processor-centric Operating Systems.
Proceedings of the 15th Workshop on Hot Topics in Operating Systems, 2015

TERAFLUX: Harnessing dataflow in next generation teradevices.
Microprocess. Microsystems, 2014

An Introduction to DF-Threads and their Execution Model.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

HPC-Aware VM Placement in Infrastructure Clouds.
Proceedings of the 2013 IEEE International Conference on Cloud Engineering, 2013

The Who, What, Why, and How of High Performance Computing in the Cloud.
Proceedings of the IEEE 5th International Conference on Cloud Computing Technology and Science, 2013

Top Picks from the 2011 Computer Architecture Conferences.
IEEE Micro, 2012

Simulating the future kilo-x86-64 core processors and their infrastructure.
Proceedings of the 2012 Spring Simulation Multiconference, 2012

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Exploring the performance and mapping of HPC applications to platforms in the cloud.
Proceedings of the 21st International Symposium on High-Performance Parallel and Distributed Computing, 2012

VLIW Processors.
Proceedings of the Encyclopedia of Parallel Computing, 2011

System-level integrated server architectures for scale-out datacenters.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

COTSon: infrastructure for full system simulation.
ACM SIGOPS Oper. Syst. Rev., 2009

How to simulate 1000 cores.
SIGARCH Comput. Archit. News, 2009

High-speed network modeling for full system simulation.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

Operating System Support for NVM+DRAM Hybrid Main Memory.
Proceedings of HotOS'09: 12th Workshop on Hot Topics in Operating Systems, 2009

An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

Combining Simulation and Virtualization through Dynamic Sampling.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Document digitization lifecycle for complex magazine collection.
Proceedings of the 2005 ACM Symposium on Document Engineering, 2005

Embedded computing - a VLIW approach to architecture, compilers, and tools.
Morgan Kaufmann, ISBN: 978-1-55860-766-8, 2005

DELI: a new run-time control point.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

A New Facility for Dynamic Control of Program Execution: DELI.
Proceedings of the Embedded Software, Second International Conference, 2002

Instruction scheduling for instruction level parallel processors.
Proc. IEEE, 2001

Lx: a technology platform for customizable VLIW embedded processing.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

The latest word in digital and media processing.
IEEE Signal Process. Mag., 1998

Custom-fit Processors: Letting Applications Define Architectures.
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Hardware solutions for fuzzy control.
Proc. IEEE, 1995

Block placement with a Boltzmann Machine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An evaluation system for distributed-time VHDL simulation.
Proceedings of the Eighth Workshop on Parallel and Distributed Simulation, 1994

Efficient implementation of the Boltzmann machine algorithm.
IEEE Trans. Neural Networks, 1993

Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems.
Parallel Comput., 1993

Delay insensitive micro-pipelined combinational logic.
Microprocess. Microprogramming, 1993

Design of a massively parallel SIMD architecture for the Boltzmann machine.
Microprocess. Microprogramming, 1993

A delay insensitive approach to the VLSI design of a DRAM controller.
Microprocess. Microprogramming, 1993

A parallel architecture for the Color Doppler flow technique in ultrasound imaging.
Microprocess. Microprogramming, 1993

An asynchronous approach to the RISC design of a micro-controller.
Microprocess. Microprogramming, 1993

An analysis of dynamic scheduling techniques for symbolic applications.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A dedicated massively parallel architecture for the Boltzmann machine.
Parallel Comput., 1992

Massive parallelism in multi-level simulation of VLSI circuits.
Integr., 1992

A non-deterministic scheduler for a software pipelining compiler.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Instruction-level Parallelism in Prolog: Analysis and Architectural Support.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

A Boltzmann Machine approach to code optimization.
Parallel Comput., 1991

An evaluation system for application specific architectures.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990