Joseph R. Shinnerl

According to our database¹, Joseph R. Shinnerl authored at least 21 papers between 1996 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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On csauthors.net:

Bibliography

2023

Locality and Utilization in Placement Suboptimality.

[BibT_eX]

[DOI]

CoRR, 2023

2018

Large-Scale Global Placement.

[BibT_eX]

Jason Cong

Joseph R. Shinnerl

Proceedings of the Handbook of Approximation Algorithms and Metaheuristics, 2018

2015

POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014

ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2014

2013

POLAR: placement based on novel rough legalization and refinement.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2008

Enhancing Placement with Multilevel Techniques.

[BibT_eX]

[DOI]

Jason Cong

Joseph R. Shinnerl

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

2007

Large-Scale Global Placement.

[BibT_eX]

[DOI]

Joseph R. Shinnerl

Jason Cong

Proceedings of the Handbook of Approximation Algorithms and Metaheuristics., 2007

Locality and Utilization in Placement Suboptimality.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

Fast floorplanning by look-ahead enabled recursive bipartitioning.

[BibT_eX]

[DOI]

Jason Cong

Michail Romesis

Joseph R. Shinnerl

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

mPL6: enhanced multilevel mixed-size placement.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

2005

Large-scale circuit placement.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

mPL6: a robust multilevel mixed-size placement engine.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Robust mixed-size placement under tight white-space constraints.

[BibT_eX]

[DOI]

Jason Cong

Michail Romesis

Joseph R. Shinnerl

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

An area-optimality study of floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Physical Design, 2004

2003

Large-Scale Circuit Placement: Gap and Promise.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

An Enhanced Multilevel Algorithm for Circuit Placement.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2000

Multilevel Optimization for Large-Scale Circuit Placement.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1996

On the Stability of Cholesky Factorization for Symmetric Quasidefinite Systems.

[BibT_eX]

[DOI]

Philip E. Gill

Michael A. Saunders

Joseph R. Shinnerl

SIAM J. Matrix Anal. Appl., 1996

Stability of Symmetric Ill-Conditioned Systems Arising in Interior Methods for Constrained Optimization.

[BibT_eX]

[DOI]

Anders Forsgren

Philip E. Gill

Joseph R. Shinnerl

SIAM J. Matrix Anal. Appl., 1996

Joseph R. Shinnerl

Timeline

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On csauthors.net:

Bibliography

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