Chris C. N. Chu
According to our database^{1},
Chris C. N. Chu
authored at least 124 papers
between 1993 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2012, "For contributions to physical design of integrated circuits".
Timeline
Legend:
Book In proceedings Article PhD thesis OtherLinks
Online presence:

on orcid.org
On csauthors.net:
Bibliography
2020
Fast Lagrangian RelaxationBased Multithreaded Gate Sizing Using Simple Timing Calibrations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
CoRR, 2020
2019
J. Electr. Comput. Eng., 2019
Leveraging Two Reference Functions in Block Bregman Proximal Gradient Descent for Nonconvex and NonLipschitz Problems.
CoRR, 2019
Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling  A Fast and Effective Approach.
Proceedings of the 2019 International Symposium on Physical Design, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
SelfAligned Double PatterningAware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 International Symposium on Physical Design, 2018
DID: Distributed Incremental Block Coordinate Descent for Nonnegative Matrix Factorization.
Proceedings of the ThirtySecond AAAI Conference on Artificial Intelligence, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
SelfAligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Proceedings of the 2017 IEEE/ACM International Conference on ComputerAided Design, 2017
2016
Encyclopedia of Algorithms, 2016
Encyclopedia of Algorithms, 2016
Detailed Placement Algorithm for VLSI Design With DoubleRow Height Standard Cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Area optimization of resilient designs guided by a mixed integer geometric program.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
POLAR: A High Performance MixedSize WirelenghDriven Placer With Density Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for Ebeam Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
TPLAware Displacementdriven Detailed Placement Refinement with Coloring Constraints.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2015
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2015
An efficient shift invariant rasterization algorithm for allangle mask patterns in ILT.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Detailed routing for spacerismetal type selfaligned double/quadruple patterning lithography.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015
2014
An Effective FloorplanGuided Placement Algorithm for LargeScale MixedSize Designs.
ACM Trans. Design Autom. Electr. Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Flexible packed stencil design with multiple shaping apertures for ebeam lithography.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
SDS: An Optimal SlackDriven Block Shaping Algorithm for FixedOutline Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IT Prof., 2013
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2013
2012
VLSI Design, 2012
VLSI Design, 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the International Symposium on Physical Design, 2012
GDRouter: interleaved global routing and detailed routing for ultimate routability.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
SafeChoice: A Novel Approach to Hypergraph Clustering for WirelengthDriven Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 2011 International Symposium on Physical Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on ComputerAided Design, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 2010 International Conference on ComputerAided Design, 2010
2009
Integr., 2009
Proceedings of the 2009 International Conference on ComputerAided Design, 2009
GREMA: Graph reduction based efficient mask assignment for double patterning technology.
Proceedings of the 2009 International Conference on ComputerAided Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
Proceedings of the Encyclopedia of Algorithms  2008 Edition, 2008
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 2008 International Conference on ComputerAided Design, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 2007 International Conference on ComputerAided Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007
2006
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASPDAC 2006, 2006
2005
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 2005 International Symposium on Physical Design, 2005
Proceedings of the 2005 International Symposium on Physical Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on ComputerAided Design, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Nonrectangular shaping and sizing of soft modules for floorplandesign improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 2004 International Symposium on Physical Design, 2004
Proceedings of the 2004 International Conference on ComputerAided Design, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Twin binary sequences: a nonredundant representation for general nonslicing floorplan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Reliab. Comput., 2003
Proceedings of the VLSISOC: From Systems to Chips, 2003
Proceedings of the 2003 International Conference on ComputerAided Design, 2003
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.
Proceedings of the 2003 Design, 2003
2002
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002
Twin binary sequences: a nonredundant representation for general nonslicing floorplan.
Proceedings of 2002 International Symposium on Physical Design, 2002
Proceedings of the 2002 Design, 2002
2001
ACM Trans. Design Autom. Electr. Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Ann. Oper. Res., 2001
2000
Proceedings of the 2000 International Symposium on Physical Design, 2000
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization.
Proceedings of the 2000 International Symposium on Physical Design, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
J. ACM, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the 1997 International Symposium on Physical Design, 1997
Proceedings of the 1997 IEEE/ACM International Conference on ComputerAided Design, 1997
1996
J. Parallel Distributed Comput., 1996
1993
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993