Chris C. N. Chu

According to our database1, Chris C. N. Chu authored at least 123 papers between 1993 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to physical design of integrated circuits".

Timeline

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Bibliography

2020
Randomized Bregman Coordinate Descent Methods for Non-Lipschitz Optimization.
CoRR, 2020

2019
CHIP: Clustering Hotspots in Layout Using Integer Programming.
J. Electrical and Computer Engineering, 2019

Leveraging Two Reference Functions in Block Bregman Proximal Gradient Descent for Non-convex and Non-Lipschitz Problems.
CoRR, 2019

Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2018
Introduction to the Special Section on Advances in Physical Design Automation.
ACM Trans. Design Autom. Electr. Syst., 2018

Area Optimization of Timing Resilient Designs Using Resynthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Pioneer Research on Mathematical Models and Methods for Physical Design.
Proceedings of the 2018 International Symposium on Physical Design, 2018

DID: Distributed Incremental Block Coordinate Descent for Nonnegative Matrix Factorization.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018

2017
Two Approaches for Timing-Driven Placement by Lagrangian Relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A Fast Incremental Cycle Ratio Algorithm.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Pin Accessibility-Driven Detailed Placement Refinement.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Rapid gate sizing with fewer iterations of Lagrangian Relaxation.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Wire Sizing.
Encyclopedia of Algorithms, 2016

Block Shaping in Floorplan.
Encyclopedia of Algorithms, 2016

Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Flip-flop clustering by weighted K-means algorithm.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Area optimization of resilient designs guided by a mixed integer geometric program.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Minimum implant area-aware placement and threshold voltage refinement.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

POLAR 3.0: An Ultrafast Global Placement Engine.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs.
ACM Trans. Design Autom. Electr. Syst., 2014

E-Beam Lithography Character and Stencil Co-Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Double patterning-aware detailed routing with mask usage balancing.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Asynchronous circuit placement by lagrangian relaxation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

POLAR 2.0: An Effective Routability-Driven Placer.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Flexible packed stencil design with multiple shaping apertures for e-beam lithography.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Fast and Effective Placement Refinement for Routability.
IEEE Trans. VLSI Syst., 2013

RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns.
IEEE Trans. VLSI Syst., 2013

SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Capturing Cognitive Fingerprints from Keystroke Dynamics.
IT Professional, 2013

POLAR: placement based on novel rough legalization and refinement.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Line Search-Based Inverse Lithography Technique for Mask Design.
VLSI Design, 2012

FastRoute: An Efficient and High-Quality Global Router.
VLSI Design, 2012

Rethinking the Wirelength Benefit of 3-D Integration.
IEEE Trans. VLSI Syst., 2012

Pad Assignment for Die-Stacking System-in-Package Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Optimal slack-driven block shaping algorithm in fixed-outline floorplanning.
Proceedings of the International Symposium on Physical Design, 2012

GDRouter: interleaved global routing and detailed routing for ultimate routability.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

RegularRoute: an efficient detailed router with regular routing patterns.
Proceedings of the 2011 International Symposium on Physical Design, 2011

MGR: Multi-level global router.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

SafeChoice: a novel clustering algorithm for wirelength-driven placement.
Proceedings of the 2010 International Symposium on Physical Design, 2010

A matching based decomposer for double patterning lithography.
Proceedings of the 2010 International Symposium on Physical Design, 2010

ITOP: integrating timing optimization within placement.
Proceedings of the 2010 International Symposium on Physical Design, 2010

An auction based pre-processing technique to determine detour in global routing.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
Handling routability in floorplan design with twin binary trees.
Integr., 2009

CROP: Fast and effective congestion refinement of placement.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

GREMA: Graph reduction based efficient mask assignment for double patterning technology.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Handling complexities in modern large-scale mixed-size placement.
Proceedings of the 46th Design Automation Conference, 2009

FastRoute 4.0: global router with efficient via minimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Practical Issues in Clock Network Design.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Clock Network Design.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Wire Sizing.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

FastRoute3.0: a fast and high quality global router based on virtual capacity.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

DeFer: deferred decision making enabled fixed-outline floorplanner.
Proceedings of the 45th Design Automation Conference, 2008

2007
Wire Retiming Problem With Net Topology Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

The coming of age of physical synthesis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
Proceedings of the 44th Design Automation Conference, 2007

IPR: An Integrated Placement and Routing Algorithm.
Proceedings of the 44th Design Automation Conference, 2007

FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

A Novel Performance-Driven Topology Design Algorithm.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

FastRoute 2.0: A High-quality and Efficient Global Router.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
Analog placement with symmetry and other placement constraints.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

FastRoute: a step to integrate global routing into placement.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A revisit to floorplan optimization by Lagrangian relaxation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Post-placement voltage island generation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Optimal cell flipping in placement and floorplanning.
Proceedings of the 43rd Design Automation Conference, 2006

FastPlace 2.0: an efficient analytical placer for mixed-mode designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

FastPlace: an analytical placer for mixed-mode designs.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Timing yield estimation using statistical static timing analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Transition time bounded low-power clock tree construction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

An efficient and effective detailed placement algorithm.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Placement constraints in floorplan design.
IEEE Trans. VLSI Syst., 2004

Fitted Elmore delay: a simple and accurate interconnect delay model.
IEEE Trans. VLSI Syst., 2004

Nonrectangular shaping and sizing of soft modules for floorplan-design improvement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Optimal gate sizing for coupling-noise reduction.
Proceedings of the 2004 International Symposium on Physical Design, 2004

FLUTE: fast lookup table based wirelength estimation technique.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Accurate and efficient flow based congestion estimation in floorplanning.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Twin binary sequences: a nonredundant representation for general nonslicing floorplan.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Bounds on the number of slicing, mosaic, and general floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Dependable Handling of Uncertainty.
Reliable Computing, 2003

Optimizing SOC Test Resources Using Dual Sequences.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Retiming with Interconnect and Gate Delay.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.
Proceedings of the 2003 Design, 2003

2002
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Twin binary sequences: a non-redundant representation for general non-slicing floorplan.
Proceedings of 2002 International Symposium on Physical Design, 2002

Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design.
Proceedings of the 2002 Design, 2002

2001
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.
ACM Trans. Design Autom. Electr. Syst., 2001

Handling soft modules in general nonslicing floorplan usingLagrangian relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

VLSI Circuit Performance Optimization by Geometric Programming.
Annals OR, 2001

2000
Floorplan area minimization using Lagrangian relaxation.
Proceedings of the 2000 International Symposium on Physical Design, 2000

A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization.
Proceedings of the 2000 International Symposium on Physical Design, 2000

1999
An efficient and optimal algorithm for simultaneous buffer and wire sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Greedy wire-sizing is linear time.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Generation of Universal Series-Parallel Boolean Functions.
J. ACM, 1999

1998
A matrix synthesis approach to thermal placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.
Proceedings of the 1998 Design, 1998

1997
Closed form solution to simultaneous buffer insertion/sizing and wire sizing.
Proceedings of the 1997 International Symposium on Physical Design, 1997

A new approach to simultaneous buffer insertion and wire sizing.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes.
J. Parallel Distributed Comput., 1996

1993
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993


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