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Jun Yan

Affiliations:
  • Mathworks Inc., Natick, MA, USA
  • Southern Illinois University Carbondale, Department of Electrical and Computer Engineering, IL, USA (former)


According to our database1, Jun Yan authored at least 18 papers between 2005 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Priority L2 cache design for time predictability.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Int. J. Embed. Syst., 2016

2012
Static Timing Analysis of Shared Caches for Multicore Processors.
[BibTeX]
[DOI]
Wei Zhang
,
Jun Yan
J. Comput. Sci. Eng., 2012

2011
An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
J. Comput. Sci. Eng., 2011

Computing and Reducing Transient Error Propagation in Registers.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
J. Comput. Sci. Eng., 2011

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
J. Comput. Sci. Eng., 2011

2010
Design and implementation of hybrid multicore simulators.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Int. J. Embed. Syst., 2010

Time-Predictable L2 Cache Design for High-Performance Real-Time Systems.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010

2009
Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications.
[BibTeX]
[DOI]
Yiqiang Ding
,
Jun Yan
,
Wei Zhang
J. Comput. Sci. Eng., 2009

Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches.
[BibTeX]
[DOI]
Wei Zhang
,
Jun Yan
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

2008
Analyzing the worst-case execution time for instruction caches with prefetching.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
ACM Trans. Embed. Comput. Syst., 2008

Exploiting virtual registers to reduce pressure on real registers.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
ACM Trans. Archit. Code Optim., 2008

A time-predictable VLIW processor and its compiler support.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Real Time Syst., 2008

WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, 2008

2007
Evaluating instruction cache vulnerability to transient errors.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
SIGARCH Comput. Archit. News, 2007

Hybrid multi-core architecture for boosting single-threaded performance.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
SIGARCH Comput. Archit. News, 2007

WCET analysis of instruction caches with prefetching.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Virtual Registers: Reducing Register Pressure Without Enlarging the Register File.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

2005
Compiler-guided register reliability improvement against soft errors.
[BibTeX]
[DOI]
Jun Yan
,
Wei Zhang
Proceedings of the EMSOFT 2005, 2005


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