Jun Yeon Won

Orcid: 0000-0001-5760-2545

According to our database1, Jun Yeon Won authored at least 12 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Method for Diagnosing Channel Damage Using FPGA Transceiver.
Proceedings of the IEEE International Test Conference, 2023

Method for Adjusting Termination Resistance Using PMU in DC Test.
Proceedings of the IEEE International Test Conference, 2023

2022
What You See is Not What You Get: Revealing Hidden Memory Mapping for Peripheral Modeling.
Proceedings of the 25th International Symposium on Research in Attacks, 2022

4.5 Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment.
Proceedings of the IEEE International Test Conference, 2022

SymLM: Predicting Function Names in Stripped Binaries via Context-Sensitive Execution-Aware Code Embeddings.
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022

2021
Development and Initial Results of a Brain PET Insert for Simultaneous 7-Tesla PET/MRI Using an FPGA-Only Signal Digitization Method.
IEEE Trans. Medical Imaging, 2021

Demo: Attacking Multi-Sensor Fusion based Localization in High-Level Autonomous Driving.
Proceedings of the IEEE Security and Privacy Workshops, 2021

2020
Drift with Devil: Security of Multi-Sensor Fusion based Localization in High-Level Autonomous Driving under GPS Spoofing (Extended Version).
CoRR, 2020

Drift with Devil: Security of Multi-Sensor Fusion based Localization in High-Level Autonomous Driving under GPS Spoofing.
Proceedings of the 29th USENIX Security Symposium, 2020

2018
Highly Integrated FPGA-Only Signal Digitization Method Using Single-Ended Memory Interface Input Receivers for Time-of-Flight PET Detectors.
IEEE Trans. Biomed. Circuits Syst., 2018

2016
Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs.
IEEE Trans. Instrum. Meas., 2016

Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.
IEEE Trans. Biomed. Circuits Syst., 2016


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