Junhui Xiang

According to our database, Junhui Xiang authored at least 5 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur Suppression for NB-IoT Applications.

Na Yan, Lei Ma, Yongxin Xu, Sizheng Chen, Xusong Liu, Junhui Xiang, Hao Min

IEEE Access, 2019

2018

An Active Tag Using Carrier Recovery Circuit for EPC Gen2 Passive UHF RFID Systems.

Tao Yang, Junhui Xiang, Yu Wang, Xi Tan, Junyu Wang, Na Yan, Lirong Zheng, Hao Min

IEEE Trans. Ind. Electron., 2018

2015

A fully logic CMOS compatible non-volatile memory for low power IoT applications.

Yu Wang, Junhui Xiang, Xianliang Chen, Tao Yang, Na Yan, Hao Min

Proceedings of the 5th International Conference on the Internet of Things, 2015

A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS.

Xusong Liu, Lei Ma, Junhui Xiang, Na Yan, Haolv Xie, Xiaowei Cai

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An asynchronous delay line TDC for ADPLL in 0.13um CMOS.

Chunhui Li, Lei Ma, Junhui Xiang, Hao Min

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015