Junlin Zhong
Orcid: 0000-0002-6395-2151
According to our database1,
Junlin Zhong
authored at least 2 papers
between 2023 and 2025.
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Collaborative distances:
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Bibliography
2025
24.3: A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2023
A 0.016mm<sup>2</sup> Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023